Girish Venkitachalam

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Strain-enhanced transistors with adjustable layouts
- Patent number 9,634,094
- Issue date Apr 25, 2017
- Altera Corporation
- Girish Venkitachalam
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit and a method to optimize strain inducing composites
- Patent number 9,484,411
- Issue date Nov 1, 2016
- Altera Corporation
- Girish Venkitachalam
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metal-insulator-metal capacitors between metal interconnect layers
- Patent number 9,331,137
- Issue date May 3, 2016
- Altera Corporation
- Deepa Ratakonda
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit and a method to optimize strain inducing composites
- Patent number 8,765,541
- Issue date Jul 1, 2014
- Altera Corporation
- Girish Venkitachalam
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Strain enhanced transistors with adjustable layouts
- Patent number 8,664,725
- Issue date Mar 4, 2014
- Altera Corporation
- Girish Venkitachalam
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Automated verification of transformational operations on a photomas...
- Patent number 8,627,264
- Issue date Jan 7, 2014
- Altera Corporation
- Girish Venkitachalam
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Integrated circuit bond pad structures
- Patent number 7,741,716
- Issue date Jun 22, 2010
- Altera Corporation
- Girish Venkitachalam
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and system for checking operation of a mask generation algor...
- Patent number 7,139,997
- Issue date Nov 21, 2006
- Altera Corporation
- Irfan Rahim
- G06 - COMPUTING CALCULATING COUNTING

Girish Venkitachalam

Person

Patents Grantslast 30 patents

Strain-enhanced transistors with adjustable layouts

Integrated circuit and a method to optimize strain inducing composites

Metal-insulator-metal capacitors between metal interconnect layers

Integrated circuit and a method to optimize strain inducing composites

Strain enhanced transistors with adjustable layouts

Automated verification of transformational operations on a photomas...

Integrated circuit bond pad structures

Method and system for checking operation of a mask generation algor...