Giuliano Gennaro Imondi

Person

Via Benucci, IT

People

Patents Grantslast 30 patents

Information Patent Grant
Memory area protection system and methods
- Patent number 9,406,388
- Issue date Aug 2, 2016
- Micron Technology, Inc.
- Luca De Santis
- G11 - INFORMATION STORAGE
Information Patent Grant
Programming methods and memories
- Patent number 8,451,661
- Issue date May 28, 2013
- Micron Technology, Inc.
- Giuliano G. Imondi
- G11 - INFORMATION STORAGE
Information Patent Grant
Programming methods and memories
- Patent number 8,139,419
- Issue date Mar 20, 2012
- Micron Technology, Inc.
- Giuliano G. Imondi
- G11 - INFORMATION STORAGE
Information Patent Grant
Pipelined burst memory access
- Patent number 7,949,844
- Issue date May 24, 2011
- Micron Technology, Inc.
- Giuliano Gennaro Imondi
- G11 - INFORMATION STORAGE
Information Patent Grant
Background block erase check for flash memories
- Patent number 7,565,587
- Issue date Jul 21, 2009
- Micron Technology, Inc.
- Giuliano Gennaro Imondi
- G11 - INFORMATION STORAGE
Information Patent Grant
Pipelined burst memory access
- Patent number 7,363,452
- Issue date Apr 22, 2008
- Micron Technology, Inc.
- Giuliano Gennaro Imondi
- G11 - INFORMATION STORAGE
Information Patent Grant
No-precharge FAMOS cell and latch circuit in a memory device
- Patent number 7,263,022
- Issue date Aug 28, 2007
- Micron Technology, Inc.
- Giuliano Gennaro Imondi
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual bus memory burst architecture
- Patent number 7,164,607
- Issue date Jan 16, 2007
- Micron Technology, Inc.
- Girolamo Gallo
- G11 - INFORMATION STORAGE
Information Patent Grant
No-precharge FAMOS cell and latch circuit in a memory device
- Patent number 7,154,800
- Issue date Dec 26, 2006
- Micron Technology, Inc.
- Giuliano Gennaro Imondi
- G11 - INFORMATION STORAGE
Information Patent Grant
Background block erase check for flash memories
- Patent number 7,117,402
- Issue date Oct 3, 2006
- Micron Technology, Inc.
- Maurizio Di Zenzo
- G11 - INFORMATION STORAGE
Information Patent Grant
Pipelined burst memory access
- Patent number 7,020,737
- Issue date Mar 28, 2006
- Micron Technology, Inc.
- Giuliano Gennaro Imondi
- G11 - INFORMATION STORAGE
Information Patent Grant
No-precharge FAMOS cell and latch circuit in a memory device
- Patent number 6,967,889
- Issue date Nov 22, 2005
- Micron Technology, Inc.
- Giuliano Gennaro Imondi
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual bus memory burst architecture
- Patent number 6,917,545
- Issue date Jul 12, 2005
- Micron Technology, Inc.
- Girolamo Gallo
- G11 - INFORMATION STORAGE
Information Patent Grant
Field memories
- Patent number 6,005,820
- Issue date Dec 21, 1999
- Texas Instruments Incorporated
- Giuliano Imondi
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit with non-volatile, variable resistor, for use in...
- Patent number 5,457,771
- Issue date Oct 10, 1995
- Texas Instruments Incorporated
- Giuliano Imondi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuitry and method for selectively switching negative voltages in...
- Patent number 5,319,604
- Issue date Jun 7, 1994
- Texas Instruments Incorporated
- Giuliano Imondi
- G11 - INFORMATION STORAGE
Information Patent Grant
Data processing system for implementing architecture of neural netw...
- Patent number 5,299,286
- Issue date Mar 29, 1994
- Texas Instruments Incorporated
- Giuliano Imondi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Learning system for a neural net of a suitable architecture, physic...
- Patent number 5,274,743
- Issue date Dec 28, 1993
- Texas Instruments Incorporated
- Giuliano Imondi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Wordline driver circuit for EEPROM memory cell
- Patent number 5,265,052
- Issue date Nov 23, 1993
- Texas Instruments Incorporated
- Sebastiano D'Arrigo
- G11 - INFORMATION STORAGE
Information Patent Grant
Driving circuitry for EEPROM memory cell
- Patent number 4,823,318
- Issue date Apr 18, 1989
- Texas Instruments Incorporated
- Sebastiano D'Arrigo
- G11 - INFORMATION STORAGE
Information Patent Grant
Electrically programmable fuse circuit for an integrated-circuit chip
- Patent number 4,823,320
- Issue date Apr 18, 1989
- Texas Instruments Incorporated
- Michael C. Smayling
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory array with an array reorganizer
- Patent number 4,760,555
- Issue date Jul 26, 1988
- Texas Instruments Incorporated
- Tito Gelsomini
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of forming a field plate in a high voltage array
- Patent number 4,736,342
- Issue date Apr 5, 1988
- Texas Instruments Incorporated
- Giuliano Imondi
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and circuit for trimming the frequency of an oscillator
- Patent number 4,723,114
- Issue date Feb 2, 1988
- Texas Instruments Incorporated
- Sebastiano D'Arrigo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Power-up control circuit including a comparator, Schmitt trigger, a...
- Patent number 4,716,322
- Issue date Dec 29, 1987
- Texas Instruments Incorporated
- Sebastiano D'Arrigo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High voltage pulse detector with controllable current consumption
- Patent number 4,706,011
- Issue date Nov 10, 1987
- Texas Instruments Incorporated
- Sossio Vergara
- G05 - CONTROLLING REGULATING
Information Patent Grant
Integrated circuit oscillator
- Patent number 4,652,837
- Issue date Mar 24, 1987
- Texas Instruments Incorporated
- Sebastiano D'Arrigo
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
PROGRAMMING METHODS AND MEMORIES
- Publication number 20120163094
- Publication date Jun 28, 2012
- Micron Technology, Inc.
- Giuliano G. Imondi
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAMMING METHODS AND MEMORIES
- Publication number 20110134702
- Publication date Jun 9, 2011
- Micron Technology, Inc.
- Giuliano G. Imondi
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Area Protection System and Methods
- Publication number 20100138623
- Publication date Jun 3, 2010
- Micron Technology, Inc.
- Luca De Santis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PIPELINED BURST MEMORY ACCESS
- Publication number 20080195795
- Publication date Aug 14, 2008
- Micron Technology, Inc.
- Giuliano Gennaro Imondi
- G11 - INFORMATION STORAGE
Information Patent Application
Background block erase check for flash memories
- Publication number 20070022332
- Publication date Jan 25, 2007
- Micron Technology, Inc.
- Giuliano Gennaro Imondi
- G11 - INFORMATION STORAGE
Information Patent Application
No-precharge FAMOS cell and latch circuit in a memory device
- Publication number 20060239099
- Publication date Oct 26, 2006
- Micron Technology, Inc.
- Giuliano Gennaro Imondi
- G11 - INFORMATION STORAGE
Information Patent Application
Pipelined burst memory access
- Publication number 20060126411
- Publication date Jun 15, 2006
- Micron Technology, Inc.
- Giuliano Gennaro Imondi
- G11 - INFORMATION STORAGE
Information Patent Application
No-precharge FAMOS cell and latch circuit in a memory device
- Publication number 20050270879
- Publication date Dec 8, 2005
- Micron Technology, Inc.
- Giuliano Gennaro Imondi
- G11 - INFORMATION STORAGE
Information Patent Application
Dual bus memory burst architecture
- Publication number 20050207233
- Publication date Sep 22, 2005
- Micron Technology, Inc.
- Girolamo Gallo
- G11 - INFORMATION STORAGE
Information Patent Application
No-precharge FAMOS cell and latch circuit in a memory device
- Publication number 20050007854
- Publication date Jan 13, 2005
- Giuliano Gennaro Imondi
- G11 - INFORMATION STORAGE
Information Patent Application
Dual bus memory burst architecture
- Publication number 20040071037
- Publication date Apr 15, 2004
- Girolamo Gallo
- G11 - INFORMATION STORAGE
Information Patent Application
Pipelined burst memory access
- Publication number 20030214854
- Publication date Nov 20, 2003
- Giuliano Gennaro Imondi
- G11 - INFORMATION STORAGE
Information Patent Application
Background block erase check for flash memories
- Publication number 20030101390
- Publication date May 29, 2003
- Maurizio Di Zenzo
- G11 - INFORMATION STORAGE

Giuliano Gennaro Imondi

Person

Patents Grantslast 30 patents

Memory area protection system and methods

Programming methods and memories

Programming methods and memories

Pipelined burst memory access

Background block erase check for flash memories

Pipelined burst memory access

No-precharge FAMOS cell and latch circuit in a memory device

Dual bus memory burst architecture

No-precharge FAMOS cell and latch circuit in a memory device

Background block erase check for flash memories

Pipelined burst memory access

No-precharge FAMOS cell and latch circuit in a memory device

Dual bus memory burst architecture

Field memories

Integrated circuit with non-volatile, variable resistor, for use in...

Circuitry and method for selectively switching negative voltages in...

Data processing system for implementing architecture of neural netw...

Learning system for a neural net of a suitable architecture, physic...

Wordline driver circuit for EEPROM memory cell

Driving circuitry for EEPROM memory cell

Electrically programmable fuse circuit for an integrated-circuit chip

Memory array with an array reorganizer

Method of forming a field plate in a high voltage array

Method and circuit for trimming the frequency of an oscillator

Power-up control circuit including a comparator, Schmitt trigger, a...

High voltage pulse detector with controllable current consumption

Integrated circuit oscillator

Patents Applicationslast 30 patents

PROGRAMMING METHODS AND MEMORIES

PROGRAMMING METHODS AND MEMORIES

Memory Area Protection System and Methods

PIPELINED BURST MEMORY ACCESS

Background block erase check for flash memories

No-precharge FAMOS cell and latch circuit in a memory device

Pipelined burst memory access

No-precharge FAMOS cell and latch circuit in a memory device

Dual bus memory burst architecture

No-precharge FAMOS cell and latch circuit in a memory device

Dual bus memory burst architecture

Pipelined burst memory access

Background block erase check for flash memories