Giuseppe Cariello

Person

Boise, ID, US

People

Patents Grantslast 30 patents

Information Patent Grant
Dynamic memory address write policy translation based on performanc...
- Patent number 12,248,705
- Issue date Mar 11, 2025
- Micron Technology, Inc.
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable types of write operations
- Patent number 12,230,232
- Issue date Feb 18, 2025
- Micron Technology, Inc.
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed power up for a memory system
- Patent number 12,223,184
- Issue date Feb 11, 2025
- Micron Technology, Inc.
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Atomic write operations
- Patent number 12,216,572
- Issue date Feb 4, 2025
- Micron Technology, Inc.
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for suspend operations
- Patent number 12,189,522
- Issue date Jan 7, 2025
- Micron Technology, Inc.
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Monitoring flash memory erase progress using erase credits
- Patent number 12,182,407
- Issue date Dec 31, 2024
- Micron Technology, Inc.
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Weighted valid address count for garbage collection
- Patent number 12,182,015
- Issue date Dec 31, 2024
- Micron Technology, Inc.
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for failure management in memory systems
- Patent number 12,159,041
- Issue date Dec 3, 2024
- Micron Technology, Inc.
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Secure key update for replay protected memory blocks
- Patent number 12,132,832
- Issue date Oct 29, 2024
- Micron Technology, Inc.
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Access operation status signaling for memory systems
- Patent number 12,124,322
- Issue date Oct 22, 2024
- Micron Technology, Inc.
- Qing Liang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Smart factory reset procedure
- Patent number 12,124,366
- Issue date Oct 22, 2024
- Micron Technology, Inc.
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Suspending operations of a memory system
- Patent number 12,105,959
- Issue date Oct 1, 2024
- Micron Technology, Inc.
- David Aaron Palmer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
NAND temperature-aware operations
- Patent number 12,099,748
- Issue date Sep 24, 2024
- Micron Technology, Inc.
- Chiara Cerafogli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using a flag to indicate whether a mapping entry points to sequenti...
- Patent number 12,099,449
- Issue date Sep 24, 2024
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Completion flag for memory operations
- Patent number 12,050,773
- Issue date Jul 30, 2024
- Micron Technology, Inc.
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Read latency and suspend modes
- Patent number 12,045,495
- Issue date Jul 23, 2024
- Micron Technology, Inc.
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Identification and storage of boot information at a memory system
- Patent number 12,019,884
- Issue date Jun 25, 2024
- Micron Technology, Inc.
- Luca Porzio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for sequential access operations
- Patent number 12,014,073
- Issue date Jun 18, 2024
- Micron Technology, Inc.
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual address encoding for logical-to-physical mapping
- Patent number 12,007,903
- Issue date Jun 11, 2024
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device error detection with improved scanning
- Patent number 12,002,521
- Issue date Jun 4, 2024
- Micron Technology, Inc.
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Secure self-purging memory partitions
- Patent number 11,989,438
- Issue date May 21, 2024
- Micron Technology, Inc.
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic status registers array
- Patent number 11,972,144
- Issue date Apr 30, 2024
- Micron Technology, Inc.
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System using a restricted operation mode memory indicator
- Patent number 11,941,268
- Issue date Mar 26, 2024
- Micron Technology, Inc.
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Atomic write operations
- Patent number 11,934,303
- Issue date Mar 19, 2024
- Micron Technology, Inc.
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Usage level identification for memory device addresses
- Patent number 11,921,627
- Issue date Mar 5, 2024
- Micron Technology, Inc.
- Luca Porzio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Determining locations in NAND memory for boot-up code
- Patent number 11,899,532
- Issue date Feb 13, 2024
- Micron Technology, Inc.
- Nitul Gohain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data recovery using barrier commands
- Patent number 11,861,216
- Issue date Jan 2, 2024
- Micron Technology, Inc.
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable verify level for a set of data in a memory device
- Patent number 11,861,177
- Issue date Jan 2, 2024
- Micron Technology, Inc.
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modified erase
- Patent number 11,836,373
- Issue date Dec 5, 2023
- Micron Technology, Inc.
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programming multi-level memory cells
- Patent number 11,817,145
- Issue date Nov 14, 2023
- Micron Technology, Inc.
- Giuseppe Cariello
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
SEGREGATING LOGICAL TO PHYSICAL MAPPINGS
- Publication number 20250117322
- Publication date Apr 10, 2025
- Micron Technology, Inc.
- Ritesh Tiwari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SMART FACTORY RESET PROCEDURE
- Publication number 20250094339
- Publication date Mar 20, 2025
- Micron Technology, Inc.
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUSPENDING OPERATIONS OF A MEMORY SYSTEM
- Publication number 20250077077
- Publication date Mar 6, 2025
- Micron Technology, Inc.
- David Aaron Palmer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SECURE KEY UPDATE FOR REPLAY PROTECTED MEMORY BLOCKS
- Publication number 20250023725
- Publication date Jan 16, 2025
- Micro Technology, Inc.
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPLETION FLAG FOR MEMORY OPERATIONS
- Publication number 20250004640
- Publication date Jan 2, 2025
- Micron Technology, Inc.
- Giuseppe CARIELLO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
READ LATENCY AND SUSPEND MODES
- Publication number 20250004664
- Publication date Jan 2, 2025
- Micron Technology, Inc.
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPRESSED LOGICAL-TO-PHYSICAL MAPPING FOR SEQUENTIALLY STORED DATA
- Publication number 20240427707
- Publication date Dec 26, 2024
- Lodestar Licensing Group LLC
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IDENTIFICATION AND STORAGE OF BOOT INFORMATION AT A MEMORY SYSTEM
- Publication number 20240402926
- Publication date Dec 5, 2024
- Micron Technology, Inc.
- Luca Porzio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR SEQUENTIAL ACCESS OPERATIONS
- Publication number 20240385771
- Publication date Nov 21, 2024
- Micron Technology, Inc.
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC STATUS REGISTERS ARRAY
- Publication number 20240345775
- Publication date Oct 17, 2024
- Micron Technology, Inc.
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WEAR LEVELING TECHNIQUES USING DATA CHARACTERISTICS
- Publication number 20240345951
- Publication date Oct 17, 2024
- Micron Technology, Inc.
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DUAL ADDRESS ENCODING FOR LOGICAL-TO-PHYSICAL MAPPING
- Publication number 20240296125
- Publication date Sep 5, 2024
- Lodestar Licensing Group LLC
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER ARBITRATION FOR SYSTEMS OF ELECTRONIC COMPONENTS
- Publication number 20240288924
- Publication date Aug 29, 2024
- Micron Technology, Inc.
- Liang Yu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA TYPE IDENTIFICATION SCHEMES FOR MEMORY SYSTEMS
- Publication number 20240289053
- Publication date Aug 29, 2024
- Micron Technology, Inc.
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND TECHNIQUES FOR UPDATING LOGICAL-TO-PHYSICAL MAPPINGS
- Publication number 20240289272
- Publication date Aug 29, 2024
- Micron Technology, Inc.
- Ritesh Tiwari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BUFFER EXPANSION FOR RANDOM WRITE OPERATIONS
- Publication number 20240281383
- Publication date Aug 22, 2024
- Micron Technology, Inc.
- Ritesh Tiwari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ATOMIC WRITE OPERATIONS
- Publication number 20240281367
- Publication date Aug 22, 2024
- Micron Technology, Inc.
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USAGE LEVEL IDENTIFICATION FOR MEMORY DEVICE ADDRESSES
- Publication number 20240281371
- Publication date Aug 22, 2024
- Micron Technology, Inc.
- Luca Porzio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-LEVEL CELL MAINTENANCE OPERATIONS
- Publication number 20240274215
- Publication date Aug 15, 2024
- Micron Technology, Inc.
- Giuseppe Cariello
- G11 - INFORMATION STORAGE
Information Patent Application
EFFICIENCY FOR CONSECUTIVE READ OPERATIONS
- Publication number 20240264745
- Publication date Aug 8, 2024
- Micron Technology, Inc.
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DETERMINING LOCATIONS IN NAND MEMORY FOR BOOT-UP CODE
- Publication number 20240241790
- Publication date Jul 18, 2024
- Micron Technology, Inc.
- Nitul Gohain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLANE DATA TRANSFER COMMANDS
- Publication number 20240231702
- Publication date Jul 11, 2024
- Micron Technology, Inc.
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPPORTUNISTIC STORAGE OF NON-WRITE-BOOSTED DATA IN WRITE BOOSTER CA...
- Publication number 20240201888
- Publication date Jun 20, 2024
- Micron Technology, Inc.
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPRESSION AND DECOMPRESSION OF TRIM DATA
- Publication number 20240053905
- Publication date Feb 15, 2024
- Micron Technology, Inc.
- Reshmi Basu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUSPENDING OPERATIONS OF A MEMORY SYSTEM
- Publication number 20240053894
- Publication date Feb 15, 2024
- Micron Technology, Inc.
- David Aaron Palmer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WRITE QUALITY IN MEMORY SYSTEMS
- Publication number 20240053895
- Publication date Feb 15, 2024
- Micron Technology, Inc.
- Nitul Gohain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURABLE TYPES OF WRITE OPERATIONS
- Publication number 20240054971
- Publication date Feb 15, 2024
- Micron Technology, Inc.
- Giuseppe Cariello
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Application
LOW-POWER BOOT-UP FOR MEMORY SYSTEMS
- Publication number 20240045596
- Publication date Feb 8, 2024
- Micron Technology, Inc.
- Reshmi Basu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WEIGHTED VALID ADDRESS COUNT FOR GARBAGE COLLECTION
- Publication number 20240045799
- Publication date Feb 8, 2024
- Micron Technology, Inc.
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DUAL ADDRESS ENCODING FOR LOGICAL-TO-PHYSICAL MAPPING
- Publication number 20240028521
- Publication date Jan 25, 2024
- Micron Technology, Inc.
- Giuseppe CARIELLO
- G06 - COMPUTING CALCULATING COUNTING

Giuseppe Cariello

Person

Patents Grantslast 30 patents

Dynamic memory address write policy translation based on performanc...

Configurable types of write operations

Distributed power up for a memory system

Atomic write operations

Techniques for suspend operations

Monitoring flash memory erase progress using erase credits

Weighted valid address count for garbage collection

Techniques for failure management in memory systems

Secure key update for replay protected memory blocks

Access operation status signaling for memory systems

Smart factory reset procedure

Suspending operations of a memory system

NAND temperature-aware operations

Using a flag to indicate whether a mapping entry points to sequenti...

Completion flag for memory operations

Read latency and suspend modes

Identification and storage of boot information at a memory system

Techniques for sequential access operations

Dual address encoding for logical-to-physical mapping

Memory device error detection with improved scanning

Secure self-purging memory partitions

Dynamic status registers array

System using a restricted operation mode memory indicator

Atomic write operations

Usage level identification for memory device addresses

Determining locations in NAND memory for boot-up code

Data recovery using barrier commands

Configurable verify level for a set of data in a memory device

Modified erase

Programming multi-level memory cells

Patents Applicationslast 30 patents

SEGREGATING LOGICAL TO PHYSICAL MAPPINGS

SMART FACTORY RESET PROCEDURE

SUSPENDING OPERATIONS OF A MEMORY SYSTEM

SECURE KEY UPDATE FOR REPLAY PROTECTED MEMORY BLOCKS

COMPLETION FLAG FOR MEMORY OPERATIONS

READ LATENCY AND SUSPEND MODES

COMPRESSED LOGICAL-TO-PHYSICAL MAPPING FOR SEQUENTIALLY STORED DATA

IDENTIFICATION AND STORAGE OF BOOT INFORMATION AT A MEMORY SYSTEM

TECHNIQUES FOR SEQUENTIAL ACCESS OPERATIONS

DYNAMIC STATUS REGISTERS ARRAY

WEAR LEVELING TECHNIQUES USING DATA CHARACTERISTICS

DUAL ADDRESS ENCODING FOR LOGICAL-TO-PHYSICAL MAPPING

POWER ARBITRATION FOR SYSTEMS OF ELECTRONIC COMPONENTS

DATA TYPE IDENTIFICATION SCHEMES FOR MEMORY SYSTEMS

SYSTEMS AND TECHNIQUES FOR UPDATING LOGICAL-TO-PHYSICAL MAPPINGS

BUFFER EXPANSION FOR RANDOM WRITE OPERATIONS

ATOMIC WRITE OPERATIONS

USAGE LEVEL IDENTIFICATION FOR MEMORY DEVICE ADDRESSES

MULTI-LEVEL CELL MAINTENANCE OPERATIONS

EFFICIENCY FOR CONSECUTIVE READ OPERATIONS

DETERMINING LOCATIONS IN NAND MEMORY FOR BOOT-UP CODE

MULTIPLANE DATA TRANSFER COMMANDS

OPPORTUNISTIC STORAGE OF NON-WRITE-BOOSTED DATA IN WRITE BOOSTER CA...

COMPRESSION AND DECOMPRESSION OF TRIM DATA

SUSPENDING OPERATIONS OF A MEMORY SYSTEM

WRITE QUALITY IN MEMORY SYSTEMS

CONFIGURABLE TYPES OF WRITE OPERATIONS

LOW-POWER BOOT-UP FOR MEMORY SYSTEMS

WEIGHTED VALID ADDRESS COUNT FOR GARBAGE COLLECTION

DUAL ADDRESS ENCODING FOR LOGICAL-TO-PHYSICAL MAPPING