Glen Arthur Wiedemeier

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Dual duty cycle correction loop for a serializer/deserializer (SerD...
- Patent number 11,804,828
- Issue date Oct 31, 2023
- International Business Machines Corporation
- Jieming Qi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Redundant clock switch
- Patent number 11,775,002
- Issue date Oct 3, 2023
- International Business Machines Corporation
- Matthew James Paschal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High-speed deserializer with programmable and timing robust data sl...
- Patent number 11,714,449
- Issue date Aug 1, 2023
- International Business Machines Corporation
- Ze Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Self-contained built-in self-test circuit with phase-shifting abili...
- Patent number 11,662,381
- Issue date May 30, 2023
- International Business Machines Corporation
- Nathan Ross Blanchard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High-speed voltage clamp for unterminated transmission lines
- Patent number 11,632,103
- Issue date Apr 18, 2023
- International Business Machines Corporation
- Chad Andrew Marquart
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Adjustable phase shifter
- Patent number 11,606,082
- Issue date Mar 14, 2023
- International Business Machines Corporation
- Yang You
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Phase rotator
- Patent number 11,558,045
- Issue date Jan 17, 2023
- International Business Machines Corporation
- Yang You
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Built-in-self-test and characterization of a high speed serial link...
- Patent number 11,528,102
- Issue date Dec 13, 2022
- International Business Machines Corporation
- Dereje Yilma
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Jitter attenuation buffer structure
- Patent number 10,958,248
- Issue date Mar 23, 2021
- International Business Machines Corporation
- Yang You
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Versatile signal detector circuit using common mode shift with all-...
- Patent number 10,826,810
- Issue date Nov 3, 2020
- International Business Machines Corporation
- Yang You
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Open-loop quadrature clock corrector and generator
- Patent number 9,912,324
- Issue date Mar 6, 2018
- International Business Machines Corporation
- Paul W. Coteus
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Frequency-domain high-speed bus signal integrity compliance model
- Patent number 9,733,305
- Issue date Aug 15, 2017
- International Business Machines Corporation
- Wiren D. Becker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Frequency-domain high-speed bus signal integrity compliance model
- Patent number 9,686,053
- Issue date Jun 20, 2017
- International Business Machines Corporation
- Wiren D. Becker
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Frequency-domain high-speed bus signal integrity compliance model
- Patent number 9,673,941
- Issue date Jun 6, 2017
- International Business Machines Corporation
- Wiren D. Becker
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Frequency-domain high-speed bus signal integrity compliance model
- Patent number 9,638,750
- Issue date May 2, 2017
- International Business Machines Corporation
- Wiren D. Becker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interface clock frequency switching using a computed insertion delay
- Patent number 9,442,512
- Issue date Sep 13, 2016
- International Business Machines Corporation
- Paul W. Coteus
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital phase detector with zero phase offset
- Patent number 8,824,573
- Issue date Sep 2, 2014
- International Business Machines Corporation
- Daniel M. Dreps
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Digital phase detector with zero phase offset
- Patent number 8,718,216
- Issue date May 6, 2014
- International Business Machines Corporation
- Daniel M. Dreps
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Clock feathered slew rate control system
- Patent number 8,674,737
- Issue date Mar 18, 2014
- International Business Machines Corporation
- Marcel A. Kossel
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-use physical architecture
- Patent number 8,543,753
- Issue date Sep 24, 2013
- International Business Machines Corporation
- Daniel M. Dreps
- G11 - INFORMATION STORAGE
Information Patent Grant
Design Structure for switching digital circuit clock net driver wit...
- Patent number 8,086,977
- Issue date Dec 27, 2011
- International Business Machines Corporation
- Jethro C. Law
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay line regulation using high-frequency micro-regulators
- Patent number 7,859,318
- Issue date Dec 28, 2010
- International Business Machines Corporation
- Daniel Dreps
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for converting between CML signal logic families
- Patent number 7,821,300
- Issue date Oct 26, 2010
- International Business Machines Corporation
- Dan P. Bernard
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multimodal memory controllers
- Patent number 7,773,689
- Issue date Aug 10, 2010
- International Business Machines Corporation
- Daniel M. Dreps
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for switching digital circuit clock net driver wi...
- Patent number 7,752,480
- Issue date Jul 6, 2010
- International Business Machines Corporation
- Jethro C. Law
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Slew rate control for driver circuit
- Patent number 7,521,968
- Issue date Apr 21, 2009
- International Business Machines Corporation
- Daniel M. Dreps
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Pulldown driver with gate protection for legacy interfaces
- Patent number 7,457,091
- Issue date Nov 25, 2008
- International Business Machines Corporation
- Dan P. Bernard
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Peaking transmission line receiver for logic signals
- Patent number 7,242,249
- Issue date Jul 10, 2007
- International Business Machines Corporation
- Daniel M. Dreps
- G11 - INFORMATION STORAGE
Information Patent Grant
Data receiver with a programmable reference voltage to optimize tim...
- Patent number 7,230,449
- Issue date Jun 12, 2007
- International Business Machines Corporation
- Daniel M. Dreps
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic line driver system for providing an optimal driver characteri...
- Patent number 7,212,035
- Issue date May 1, 2007
- International Business Machines Corporation
- Daniel M. Dreps
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Active Inductor Peaking Buffer with Output Common Mode Control
- Publication number 20250007477
- Publication date Jan 2, 2025
- International Business Machines Corporation
- Dereje Yilma
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MULTI-PHASE CLOCK GENERATION CIRCUIT WITH DIGITAL CALIBRATION
- Publication number 20250007498
- Publication date Jan 2, 2025
- International Business Machines Corporation
- David M. Friend
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DUAL DUTY CYCLE CORRECTION LOOP FOR A SERIALIZER/DESERIALIZER (SERD...
- Publication number 20230268908
- Publication date Aug 24, 2023
- International Business Machines Corporation
- Jieming Qi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
THERMALLY COUPLED AWARE DEVICE PLACEMENT
- Publication number 20230214573
- Publication date Jul 6, 2023
- International Business Machines Corporation
- Akil Khamisi Sutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH-SPEED DESERIALIZER WITH PROGRAMMABLE AND TIMING ROBUST DATA SL...
- Publication number 20230099810
- Publication date Mar 30, 2023
- International Business Machines Corporation
- Ze Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH-SPEED VOLTAGE CLAMP FOR UNTERMINATED TRANSMISSION LINES
- Publication number 20230088871
- Publication date Mar 23, 2023
- International Business Machines Corporation
- Chad Andrew Marquart
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SELF-CONTAINED BUILT-IN SELF-TEST CIRCUIT WITH PHASE-SHIFTING ABILI...
- Publication number 20230055935
- Publication date Feb 23, 2023
- International Business Machines Corporation
- Nathan Ross Blanchard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUNDANT CLOCK SWITCH
- Publication number 20230035405
- Publication date Feb 2, 2023
- International Business Machines Corporation
- Matthew James Paschal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PHASE ROTATOR
- Publication number 20220416774
- Publication date Dec 29, 2022
- International Business Machines Corporation
- Yang YOU
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ADJUSTABLE PHASE SHIFTER
- Publication number 20220376677
- Publication date Nov 24, 2022
- International Business Machines Corporation
- Yang YOU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPEN-LOOP QUADRATURE CLOCK CORRECTOR AND GENERATOR
- Publication number 20170063353
- Publication date Mar 2, 2017
- International Business Machines Corporation
- Paul W. COTEUS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FREQUENCY-DOMAIN HIGH-SPEED BUS SIGNAL INTEGRITY COMPLIANCE MODEL
- Publication number 20160352473
- Publication date Dec 1, 2016
- International Business Machines Corporation
- Wiren D. Becker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FREQUENCY-DOMAIN HIGH-SPEED BUS SIGNAL INTEGRITY COMPLIANCE MODEL
- Publication number 20160349319
- Publication date Dec 1, 2016
- International Business Machines Corporation
- Wiren D. Becker
- G01 - MEASURING TESTING
Information Patent Application
FREQUENCY-DOMAIN HIGH-SPEED BUS SIGNAL INTEGRITY COMPLIANCE MODEL
- Publication number 20160349325
- Publication date Dec 1, 2016
- International Business Machines Corporation
- Wiren D. Becker
- G01 - MEASURING TESTING
Information Patent Application
FREQUENCY-DOMAIN HIGH-SPEED BUS SIGNAL INTEGRITY COMPLIANCE MODEL
- Publication number 20160350195
- Publication date Dec 1, 2016
- International Business Machines Corporation
- Wiren D. Becker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIGITAL PHASE DETECTOR WITH ZERO PHASE OFFSET
- Publication number 20140153682
- Publication date Jun 5, 2014
- International Business Machines Corporation
- Daniel M. Dreps
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
CLOCK FEATHERED SLEW RATE CONTROL SYSTEM
- Publication number 20140070864
- Publication date Mar 13, 2014
- International Business Machines Corporation
- Marcel A. Kossel
- G11 - INFORMATION STORAGE
Information Patent Application
DIGITAL PHASE DETECTOR WITH ZERO PHASE OFFSET
- Publication number 20130077724
- Publication date Mar 28, 2013
- International Business Machines Corporation
- Daniel M. Dreps
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
MULTI-USE PHYSICAL ARCHITECTURE
- Publication number 20120260016
- Publication date Oct 11, 2012
- International Business Machines Corporation
- Daniel M. Dreps
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Method for Converting Between CML Signal Logic Families
- Publication number 20100134145
- Publication date Jun 3, 2010
- International Business Machines
- Dan P. Bernard
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DELAY LINE REGULATION USING HIGH-FREQUENCY MICRO-REGULATORS
- Publication number 20090206952
- Publication date Aug 20, 2009
- Daniel Dreps
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Design Structure for Switching Digital Circuit Clock Net Driver Wit...
- Publication number 20080301606
- Publication date Dec 4, 2008
- International Business Machines Corporation
- Jethro C. Law
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multimodal Memory Controllers
- Publication number 20080189455
- Publication date Aug 7, 2008
- Daniel M. Dreps
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PULLDOWN DRIVER WITH GATE PROTECTION FOR LEGACY INTERFACES
- Publication number 20080137250
- Publication date Jun 12, 2008
- International Business Machines Corporation
- Dan P. Bernard
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
System and Method for Switching Digital Circuit Clock Net Driver Wi...
- Publication number 20080046776
- Publication date Feb 21, 2008
- Jethro C. Law
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Peaking transmission line receiver for logic signals
- Publication number 20060181348
- Publication date Aug 17, 2006
- Daniel M. Dreps
- G11 - INFORMATION STORAGE
Information Patent Application
Circuit for optimizing the duty cycle of a received clock transmitt...
- Publication number 20060181320
- Publication date Aug 17, 2006
- International Business Machines Corporation
- Daniel M. Dreps
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Slew rate control for driver circuit
- Publication number 20060181302
- Publication date Aug 17, 2006
- International Business Machines Corporation
- Daniel M. Dreps
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Data receiver with a programmable reference voltage to optimize tim...
- Publication number 20060181303
- Publication date Aug 17, 2006
- Daniel M. Dreps
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Logic line driver system for providing an optimal driver characteri...
- Publication number 20060181304
- Publication date Aug 17, 2006
- International Business Machines Corporation
- Daniel M. Dreps
- H03 - BASIC ELECTRONIC CIRCUITRY

Glen Arthur Wiedemeier

Person

Patents Grantslast 30 patents

Dual duty cycle correction loop for a serializer/deserializer (SerD...

Redundant clock switch

High-speed deserializer with programmable and timing robust data sl...

Self-contained built-in self-test circuit with phase-shifting abili...

High-speed voltage clamp for unterminated transmission lines

Adjustable phase shifter

Phase rotator

Built-in-self-test and characterization of a high speed serial link...

Jitter attenuation buffer structure

Versatile signal detector circuit using common mode shift with all-...

Open-loop quadrature clock corrector and generator

Frequency-domain high-speed bus signal integrity compliance model

Frequency-domain high-speed bus signal integrity compliance model

Frequency-domain high-speed bus signal integrity compliance model

Frequency-domain high-speed bus signal integrity compliance model

Interface clock frequency switching using a computed insertion delay

Digital phase detector with zero phase offset

Digital phase detector with zero phase offset

Clock feathered slew rate control system

Multi-use physical architecture

Design Structure for switching digital circuit clock net driver wit...

Delay line regulation using high-frequency micro-regulators

System and method for converting between CML signal logic families

Multimodal memory controllers

System and method for switching digital circuit clock net driver wi...

Slew rate control for driver circuit

Pulldown driver with gate protection for legacy interfaces

Peaking transmission line receiver for logic signals

Data receiver with a programmable reference voltage to optimize tim...

Logic line driver system for providing an optimal driver characteri...

Patents Applicationslast 30 patents

Active Inductor Peaking Buffer with Output Common Mode Control

MULTI-PHASE CLOCK GENERATION CIRCUIT WITH DIGITAL CALIBRATION

DUAL DUTY CYCLE CORRECTION LOOP FOR A SERIALIZER/DESERIALIZER (SERD...

THERMALLY COUPLED AWARE DEVICE PLACEMENT

HIGH-SPEED DESERIALIZER WITH PROGRAMMABLE AND TIMING ROBUST DATA SL...

HIGH-SPEED VOLTAGE CLAMP FOR UNTERMINATED TRANSMISSION LINES

SELF-CONTAINED BUILT-IN SELF-TEST CIRCUIT WITH PHASE-SHIFTING ABILI...

REDUNDANT CLOCK SWITCH

PHASE ROTATOR

ADJUSTABLE PHASE SHIFTER

OPEN-LOOP QUADRATURE CLOCK CORRECTOR AND GENERATOR

FREQUENCY-DOMAIN HIGH-SPEED BUS SIGNAL INTEGRITY COMPLIANCE MODEL

FREQUENCY-DOMAIN HIGH-SPEED BUS SIGNAL INTEGRITY COMPLIANCE MODEL

FREQUENCY-DOMAIN HIGH-SPEED BUS SIGNAL INTEGRITY COMPLIANCE MODEL

FREQUENCY-DOMAIN HIGH-SPEED BUS SIGNAL INTEGRITY COMPLIANCE MODEL

DIGITAL PHASE DETECTOR WITH ZERO PHASE OFFSET

CLOCK FEATHERED SLEW RATE CONTROL SYSTEM

DIGITAL PHASE DETECTOR WITH ZERO PHASE OFFSET

MULTI-USE PHYSICAL ARCHITECTURE

System and Method for Converting Between CML Signal Logic Families

DELAY LINE REGULATION USING HIGH-FREQUENCY MICRO-REGULATORS

Design Structure for Switching Digital Circuit Clock Net Driver Wit...

Multimodal Memory Controllers

PULLDOWN DRIVER WITH GATE PROTECTION FOR LEGACY INTERFACES

System and Method for Switching Digital Circuit Clock Net Driver Wi...

Peaking transmission line receiver for logic signals

Circuit for optimizing the duty cycle of a received clock transmitt...

Slew rate control for driver circuit

Data receiver with a programmable reference voltage to optimize tim...

Logic line driver system for providing an optimal driver characteri...