Glenn E. Starnes

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Area-efficient scalable memory read-data multiplexing and latching
- Patent number 12,130,654
- Issue date Oct 29, 2024
- Intel Corporation
- Amir Javidi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Area-efficient scalable memory read-data multiplexing and latching
- Patent number 11,619,963
- Issue date Apr 4, 2023
- Intel Corporation
- Amir Javidi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Area-efficient scalable memory read-data multiplexing and latching
- Patent number 11,029,720
- Issue date Jun 8, 2021
- Intel Corporation
- Amir Javidi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bypass system and method that mimics clock to data memory read timing
- Patent number 9,263,100
- Issue date Feb 16, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Bradley J. Garni
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory having a dummy bitline for timing control
- Patent number 7,746,716
- Issue date Jun 29, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Mark W. Jetton
- G11 - INFORMATION STORAGE
Information Patent Grant
Self-timed memory having common timing control circuit and method t...
- Patent number 7,518,947
- Issue date Apr 14, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Glenn E. Starnes
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple block memory with complementary data path
- Patent number 7,397,722
- Issue date Jul 8, 2008
- FREESCALE SEMICONDUCTOR, INC.
- Glenn E. Starnes
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit memory having a fuse detect circuit and method t...
- Patent number 6,157,583
- Issue date Dec 5, 2000
- Motorola, Inc.
- Glenn E. Starnes
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory utilizing a programmable delay to control address buffers
- Patent number 6,108,266
- Issue date Aug 22, 2000
- Motorola, Inc.
- William Robert Weier
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit memory having a power supply independent input b...
- Patent number 5,554,942
- Issue date Sep 10, 1996
- Motorola Inc.
- Lawrence N. Herr
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
AREA-EFFICIENT SCALABLE MEMORY READ-DATA MULTIPLEXING AND LATCHING
- Publication number 20230137508
- Publication date May 4, 2023
- Intel Corporation
- Amir JAVIDI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AREA-EFFICIENT SCALABLE MEMORY READ-DATA MULTIPLEXING AND LATCHING
- Publication number 20210294374
- Publication date Sep 23, 2021
- Intel Corporation
- Amir JAVIDI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AREA-EFFICIENT SCALABLE MEMORY READ-DATA MULTIPLEXING AND LATCHING
- Publication number 20200333825
- Publication date Oct 22, 2020
- Intel Corporation
- Amir JAVIDI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BYPASS SYSTEM AND METHOD THAT MIMICS CLOCK TO DATA MEMORY READ TIMING
- Publication number 20150155017
- Publication date Jun 4, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Bradley J. Garni
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY HAVING A DUMMY BITLINE FOR TIMING CONTROL
- Publication number 20080205176
- Publication date Aug 28, 2008
- Mark W. Jetton
- G11 - INFORMATION STORAGE
Information Patent Application
SELF-TIMED MEMORY HAVING COMMON TIMING CONTROL CIRCUIT AND METHOD T...
- Publication number 20080080297
- Publication date Apr 3, 2008
- Glenn E. Starnes
- G11 - INFORMATION STORAGE

Glenn E. Starnes

Person

Patents Grantslast 30 patents

Area-efficient scalable memory read-data multiplexing and latching

Area-efficient scalable memory read-data multiplexing and latching

Area-efficient scalable memory read-data multiplexing and latching

Bypass system and method that mimics clock to data memory read timing

Memory having a dummy bitline for timing control

Self-timed memory having common timing control circuit and method t...

Multiple block memory with complementary data path

Integrated circuit memory having a fuse detect circuit and method t...

Memory utilizing a programmable delay to control address buffers

Integrated circuit memory having a power supply independent input b...

Patents Applicationslast 30 patents

AREA-EFFICIENT SCALABLE MEMORY READ-DATA MULTIPLEXING AND LATCHING

AREA-EFFICIENT SCALABLE MEMORY READ-DATA MULTIPLEXING AND LATCHING

AREA-EFFICIENT SCALABLE MEMORY READ-DATA MULTIPLEXING AND LATCHING

BYPASS SYSTEM AND METHOD THAT MIMICS CLOCK TO DATA MEMORY READ TIMING

MEMORY HAVING A DUMMY BITLINE FOR TIMING CONTROL

SELF-TIMED MEMORY HAVING COMMON TIMING CONTROL CIRCUIT AND METHOD T...