Glenn Hinton

Person

People

Patents Grantslast 30 patents

Information Patent Grant
Dynamic partial power down of memory-side cache in a 2-level memory...
- Patent number 11,200,176
- Issue date Dec 14, 2021
- Intel Corporation
- Raj K Ramanujan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for implementing a multi-level memory hierarch...
- Patent number 11,132,298
- Issue date Sep 28, 2021
- Intel Corporation
- Raj K. Ramanujan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic partial power down of memory-side cache in a 2-level memory...
- Patent number 10,795,823
- Issue date Oct 6, 2020
- Intel Corporation
- Raj K Ramanujan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for implementing a multi-level memory hierarchy
- Patent number 10,719,443
- Issue date Jul 21, 2020
- Intel Corporation
- Raj K. Ramanujan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to suspend and resume computing systems
- Patent number 10,564,986
- Issue date Feb 18, 2020
- Intel Corporation
- Michael A. Rothman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Two-level system main memory
- Patent number 10,365,832
- Issue date Jul 30, 2019
- Intel Corporation
- Eric J. Dahlen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for implementing a multi-level memory hierarchy
- Patent number 10,241,912
- Issue date Mar 26, 2019
- Intel Corporation
- Raj K. Ramanujan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple register memory access instructions, processors, methods,...
- Patent number 10,170,165
- Issue date Jan 1, 2019
- Intel Corporation
- Glenn Hinton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple register memory access instructions, processors, methods,...
- Patent number 10,163,468
- Issue date Dec 25, 2018
- Intel Corporation
- Glenn Hinton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple register memory access instructions, processors, methods,...
- Patent number 10,153,011
- Issue date Dec 11, 2018
- Intel Corporation
- Glenn Hinton
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple register memory access instructions, processors, methods,...
- Patent number 10,153,012
- Issue date Dec 11, 2018
- Intel Corporation
- Glenn Hinton
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple register memory access instructions, processors, methods,...
- Patent number 10,141,033
- Issue date Nov 27, 2018
- Intel Corporation
- Glenn Hinton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for implementing a multi-level memory hierarch...
- Patent number 10,102,126
- Issue date Oct 16, 2018
- Intel Corporation
- Raj K. Ramanujan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple register memory access instructions, processors, methods,...
- Patent number 10,102,888
- Issue date Oct 16, 2018
- Intel Corporation
- Glenn Hinton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Replacement of a block with a compressed block to increase capacity...
- Patent number 10,048,868
- Issue date Aug 14, 2018
- Intel Corporation
- Alaa R. Alameldeen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple register memory access instructions, processors, methods,...
- Patent number 9,786,338
- Issue date Oct 10, 2017
- Intel Corporation
- Glenn Hinton
- G11 - INFORMATION STORAGE
Information Patent Grant
Instruction emulation processors, methods, and systems
- Patent number 9,703,562
- Issue date Jul 11, 2017
- Intel Corporation
- William C. Rash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Two-level system main memory
- Patent number 9,690,493
- Issue date Jun 27, 2017
- Intel Corporation
- Eric J. Dahlen
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for implementing a multi-level memory hierarchy
- Patent number 9,600,416
- Issue date Mar 21, 2017
- Intel Corporation
- Raj K. Ramanujan
- G11 - INFORMATION STORAGE
Information Patent Grant
Controlling non-redundant execution in a redundant multithreading (...
- Patent number 9,594,648
- Issue date Mar 14, 2017
- Intel Corporation
- Glenn J. Hinton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
QoS based binary translation and application streaming
- Patent number 9,525,586
- Issue date Dec 20, 2016
- Intel Corporation
- Bharath Muthiah
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for store durability and ordering in a persist...
- Patent number 9,423,959
- Issue date Aug 23, 2016
- Intel Corporation
- Subramanya R. Dulloor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple register memory access instructions, processors, methods,...
- Patent number 9,424,034
- Issue date Aug 23, 2016
- Intel Corporation
- Glenn Hinton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bad block management mechanism
- Patent number 9,418,700
- Issue date Aug 16, 2016
- Intel Corporation
- Raj K. Ramanujan
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for implementing a multi-level memory hierarch...
- Patent number 9,378,142
- Issue date Jun 28, 2016
- Intel Corporation
- Raj K. Ramanujan
- G11 - INFORMATION STORAGE
Information Patent Grant
Adaptive queuing of a cache for a processing element
- Patent number 9,146,873
- Issue date Sep 29, 2015
- Intel Corporation
- Anil Vasudevan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Machine check architecture execution environment for non-microcoded...
- Patent number 9,141,461
- Issue date Sep 22, 2015
- Intel Corporation
- Willam C. Rash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Two-level system main memory
- Patent number 9,087,584
- Issue date Jul 21, 2015
- Intel Corporation
- Eric J. Dahlen
- G11 - INFORMATION STORAGE
Information Patent Grant
Obtaining data for redundant multithreading (RMT) execution
- Patent number 9,081,688
- Issue date Jul 14, 2015
- Intel Corporation
- Glenn J. Hinton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor having execution core sections operating at different clo...
- Patent number RE45487
- Issue date Apr 21, 2015
- Intel Corporation
- David J. Sager
- 713 - Electrical computers and digital processing systems: support

Patents Applicationslast 30 patents

Information Patent Application
DYNAMIC PARTIAL POWER DOWN OF MEMORY-SIDE CACHE IN A 2-LEVEL MEMORY...
- Publication number 20210056035
- Publication date Feb 25, 2021
- Intel Corporation
- Raj K. RAMANUJAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TWO-LEVEL SYSTEM MAIN MEMORY
- Publication number 20190243558
- Publication date Aug 8, 2019
- Intel Corporation
- Eric J. Dahlen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCHY
- Publication number 20190220406
- Publication date Jul 18, 2019
- Intel Corporation
- Raj K. RAMANUJAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSLATION TABLE ENTRY PREFETCHING IN DYNAMIC BINARY TRANSLATION B...
- Publication number 20190179766
- Publication date Jun 13, 2019
- Intel Corporation
- Girish Venkatasubramanian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCH...
- Publication number 20180341588
- Publication date Nov 29, 2018
- Intel Corporation
- Raj K. RAMANUJAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO SUSPEND AND RESUME COMPUTING SYSTEMS
- Publication number 20180181411
- Publication date Jun 28, 2018
- Intel Corporation
- Michael A. Rothman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE REGISTER MEMORY ACCESS INSTRUCTIONS, PROCESSORS, METHODS,...
- Publication number 20180122431
- Publication date May 3, 2018
- lntel Corporation
- Glenn Hinton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE REGISTER MEMORY ACCESS INSTRUCTIONS, PROCESSORS, METHODS,...
- Publication number 20180122433
- Publication date May 3, 2018
- lntel Corporation
- Glenn Hinton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE REGISTER MEMORY ACCESS INSTRUCTIONS, PROCESSORS, METHODS,...
- Publication number 20180122432
- Publication date May 3, 2018
- lntel Corporation
- Glenn Hinton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE REGISTER MEMORY ACCESS INSTRUCTIONS, PROCESSORS, METHODS,...
- Publication number 20180122429
- Publication date May 3, 2018
- lntel Corporation
- Glenn Hinton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE REGISTER MEMORY ACCESS INSTRUCTIONS, PROCESSORS, METHODS,...
- Publication number 20180122430
- Publication date May 3, 2018
- lntel Corporation
- Glenn Hinton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELECTIVE DATA COMPRESSION/DECOMPRESSION FOR INTERMEMORY TRANSFER I...
- Publication number 20180095674
- Publication date Apr 5, 2018
- Intel Corporation
- Alaa R. ALAMELDEEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USING COMPRESSION TO INCREASE CAPACITY OF A MEMORY-SIDE CACHE WITH...
- Publication number 20180088822
- Publication date Mar 29, 2018
- Intel Corporation
- Alaa R. Alameldeen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE REGISTER MEMORY ACCESS INSTRUCTIONS, PROCESSORS, METHODS,...
- Publication number 20180033468
- Publication date Feb 1, 2018
- lntel Corporation
- Glenn Hinton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TWO-LEVEL SYSTEM MAIN MEMORY
- Publication number 20180004432
- Publication date Jan 4, 2018
- Intel Corporation
- Eric J. Dahlen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCHY
- Publication number 20170249250
- Publication date Aug 31, 2017
- Intel Corporation
- Raj K. RAMANUJAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCH...
- Publication number 20170031821
- Publication date Feb 2, 2017
- Raj K. Ramanujan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE REGISTER MEMORY ACCESS INSTRUCTIONS, PROCESSORS, METHODS,...
- Publication number 20160358636
- Publication date Dec 8, 2016
- lntel Corporation
- Glenn Hinton
- G11 - INFORMATION STORAGE
Information Patent Application
TWO-LEVEL SYSTEM MAIN MEMORY
- Publication number 20160041772
- Publication date Feb 11, 2016
- Intel Corporation
- Eric J. Dahlen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPCODE TRAPPING
- Publication number 20150186140
- Publication date Jul 2, 2015
- Bret L. Toll
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE REGISTER MEMORY ACCESS INSTRUCTIONS, PROCESSORS, METHODS,...
- Publication number 20150006848
- Publication date Jan 1, 2015
- Intel Corporation
- Glenn Hinton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR STORE DURABILITY AND ORDERING IN A PERSIST...
- Publication number 20150006834
- Publication date Jan 1, 2015
- Subramanya R. DULLOOR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MACHINE CHECK ARCHITECTURE EXECUTION ENVIRONMENT FOR NON-MICROCODED...
- Publication number 20140380085
- Publication date Dec 25, 2014
- Willam C. Rash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TWO-LEVEL SYSTEM MAIN MEMORY
- Publication number 20140351660
- Publication date Nov 27, 2014
- Eric J. DAHLEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METADATA MANAGEMENT AND SUPPORT FOR PHASE CHANGE MEMORY WITH SWITCH...
- Publication number 20140317337
- Publication date Oct 23, 2014
- Leena K. Puthiyedath
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC PARTIAL POWER DOWN OF MEMORY-SIDE CACHE IN A 2-LEVEL MEMO...
- Publication number 20140304475
- Publication date Oct 9, 2014
- Raj K Ramanujan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION EMULATION PROCESSORS, METHODS, AND SYSTEMS
- Publication number 20140281399
- Publication date Sep 18, 2014
- William C. Rash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR IMPLEMENTING TRANSACTIONAL MEMORY
- Publication number 20140281236
- Publication date Sep 18, 2014
- William C. Rash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
QOS BASED BINARY TRANSLATION AND APPLICATION STREAMING
- Publication number 20140281008
- Publication date Sep 18, 2014
- Bharath Muthiah
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCHY
- Publication number 20140129767
- Publication date May 8, 2014
- Raj K Ramanujan
- G06 - COMPUTING CALCULATING COUNTING

Glenn Hinton

Person

Patents Grantslast 30 patents

Dynamic partial power down of memory-side cache in a 2-level memory...

Apparatus and method for implementing a multi-level memory hierarch...

Dynamic partial power down of memory-side cache in a 2-level memory...

Apparatus and method for implementing a multi-level memory hierarchy

Methods and apparatus to suspend and resume computing systems

Two-level system main memory

Apparatus and method for implementing a multi-level memory hierarchy

Multiple register memory access instructions, processors, methods,...

Multiple register memory access instructions, processors, methods,...

Multiple register memory access instructions, processors, methods,...

Multiple register memory access instructions, processors, methods,...

Multiple register memory access instructions, processors, methods,...

Apparatus and method for implementing a multi-level memory hierarch...

Multiple register memory access instructions, processors, methods,...

Replacement of a block with a compressed block to increase capacity...

Multiple register memory access instructions, processors, methods,...

Instruction emulation processors, methods, and systems

Two-level system main memory

Apparatus and method for implementing a multi-level memory hierarchy

Controlling non-redundant execution in a redundant multithreading (...

QoS based binary translation and application streaming

Method and apparatus for store durability and ordering in a persist...

Multiple register memory access instructions, processors, methods,...

Bad block management mechanism

Apparatus and method for implementing a multi-level memory hierarch...

Adaptive queuing of a cache for a processing element

Machine check architecture execution environment for non-microcoded...

Two-level system main memory

Obtaining data for redundant multithreading (RMT) execution

Processor having execution core sections operating at different clo...

Patents Applicationslast 30 patents

DYNAMIC PARTIAL POWER DOWN OF MEMORY-SIDE CACHE IN A 2-LEVEL MEMORY...

TWO-LEVEL SYSTEM MAIN MEMORY

APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCHY

TRANSLATION TABLE ENTRY PREFETCHING IN DYNAMIC BINARY TRANSLATION B...

APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCH...

METHODS AND APPARATUS TO SUSPEND AND RESUME COMPUTING SYSTEMS

MULTIPLE REGISTER MEMORY ACCESS INSTRUCTIONS, PROCESSORS, METHODS,...

MULTIPLE REGISTER MEMORY ACCESS INSTRUCTIONS, PROCESSORS, METHODS,...

MULTIPLE REGISTER MEMORY ACCESS INSTRUCTIONS, PROCESSORS, METHODS,...

MULTIPLE REGISTER MEMORY ACCESS INSTRUCTIONS, PROCESSORS, METHODS,...

MULTIPLE REGISTER MEMORY ACCESS INSTRUCTIONS, PROCESSORS, METHODS,...

SELECTIVE DATA COMPRESSION/DECOMPRESSION FOR INTERMEMORY TRANSFER I...

USING COMPRESSION TO INCREASE CAPACITY OF A MEMORY-SIDE CACHE WITH...

MULTIPLE REGISTER MEMORY ACCESS INSTRUCTIONS, PROCESSORS, METHODS,...

TWO-LEVEL SYSTEM MAIN MEMORY

APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCHY

APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCH...

MULTIPLE REGISTER MEMORY ACCESS INSTRUCTIONS, PROCESSORS, METHODS,...

TWO-LEVEL SYSTEM MAIN MEMORY

OPCODE TRAPPING

MULTIPLE REGISTER MEMORY ACCESS INSTRUCTIONS, PROCESSORS, METHODS,...

METHOD AND APPARATUS FOR STORE DURABILITY AND ORDERING IN A PERSIST...

MACHINE CHECK ARCHITECTURE EXECUTION ENVIRONMENT FOR NON-MICROCODED...

TWO-LEVEL SYSTEM MAIN MEMORY

METADATA MANAGEMENT AND SUPPORT FOR PHASE CHANGE MEMORY WITH SWITCH...

DYNAMIC PARTIAL POWER DOWN OF MEMORY-SIDE CACHE IN A 2-LEVEL MEMO...

INSTRUCTION EMULATION PROCESSORS, METHODS, AND SYSTEMS

SYSTEMS AND METHODS FOR IMPLEMENTING TRANSACTIONAL MEMORY

QOS BASED BINARY TRANSLATION AND APPLICATION STREAMING

APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCHY