Gokul Kumar

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Manufacturing process for separating logic and memory array
- Patent number 10,930,607
- Issue date Feb 23, 2021
- Western Digital Technologies, Inc.
- Hem Takiar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bifurcated memory die module semiconductor device
- Patent number 10,923,462
- Issue date Feb 16, 2021
- Western Digital Technologies, Inc.
- Toshiki Hirano
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dedicated termination dies for memory systems
- Patent number 10,637,533
- Issue date Apr 28, 2020
- Western Digital Technologies, Inc.
- John Thomas Contreras
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Manufacturing process for separating logic and memory array
- Patent number 10,522,489
- Issue date Dec 31, 2019
- Western Digital Technologies, Inc.
- Hem Takiar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device including dual pad wire bond interconnection
- Patent number 10,483,239
- Issue date Nov 19, 2019
- SanDisk Semiconductor (Shanghai) Co. Ltd.
- Junrong Yan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transmission line optimization for multi-die systems
- Patent number 10,468,073
- Issue date Nov 5, 2019
- SanDisk Technologies LLC
- John Thomas Contreras
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-volatile memory system with wide I/O memory die
- Patent number 10,381,327
- Issue date Aug 13, 2019
- SanDisk Technologies LLC
- Venkatesh P. Ramachandra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Wire bonded wide I/O semiconductor device
- Patent number 10,249,592
- Issue date Apr 2, 2019
- SanDisk Technologies LLC
- Michael Mostovoy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wire bonded wide I/O semiconductor device
- Patent number 9,899,347
- Issue date Feb 20, 2018
- SanDisk Technologies LLC
- Michael Mostovoy
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
MANUFACTURING PROCESS FOR SEPARATING LOGIC AND MEMORY ARRAY
- Publication number 20200126936
- Publication date Apr 23, 2020
- Western Digital Technologies, Inc.
- Hem Takiar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEDICATED TERMINATION DIES FOR MEMORY SYSTEMS
- Publication number 20200106478
- Publication date Apr 2, 2020
- Western Digital Technologies, Inc.
- John Thomas Contreras
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MANUFACTURING PROCESS FOR SEPARATING LOGIC AND MEMORY ARRAY
- Publication number 20200006268
- Publication date Jan 2, 2020
- Western Digital Technologies, Inc.
- Hem Takiar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BIFURCATED MEMORY DIE MODULE SEMICONDUCTOR DEVICE
- Publication number 20190341375
- Publication date Nov 7, 2019
- Western Digital Technologies, Inc.
- Toshiki Hirano
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSMISSION LINE OPTIMIZATION FOR MULTI-DIE SYSTEMS
- Publication number 20190206450
- Publication date Jul 4, 2019
- SanDisk Technologies LLC
- John Thomas Contreras
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE INCLUDING DUAL PAD WIRE BOND INTERCONNECTION
- Publication number 20180190621
- Publication date Jul 5, 2018
- Sandisk Semiconductor (Shanghai) Co., Ltd.
- Junrong Yan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WIRE BONDED WIDE I/O SEMICONDUCTOR DEVICE
- Publication number 20180174996
- Publication date Jun 21, 2018
- SanDisk Technologies LLC
- Michael Mostovoy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NON-VOLATILE MEMORY SYSTEM WITH WIDE I/O MEMORY DIE
- Publication number 20180102344
- Publication date Apr 12, 2018
- SanDisk Technologies LLC
- Venkatesh P. Ramachandra
- G11 - INFORMATION STORAGE

Gokul Kumar

Person

Patents Grantslast 30 patents

Manufacturing process for separating logic and memory array

Bifurcated memory die module semiconductor device

Dedicated termination dies for memory systems

Manufacturing process for separating logic and memory array

Semiconductor device including dual pad wire bond interconnection

Transmission line optimization for multi-die systems

Non-volatile memory system with wide I/O memory die

Wire bonded wide I/O semiconductor device

Wire bonded wide I/O semiconductor device

Patents Applicationslast 30 patents

MANUFACTURING PROCESS FOR SEPARATING LOGIC AND MEMORY ARRAY

DEDICATED TERMINATION DIES FOR MEMORY SYSTEMS

MANUFACTURING PROCESS FOR SEPARATING LOGIC AND MEMORY ARRAY

BIFURCATED MEMORY DIE MODULE SEMICONDUCTOR DEVICE

TRANSMISSION LINE OPTIMIZATION FOR MULTI-DIE SYSTEMS

SEMICONDUCTOR DEVICE INCLUDING DUAL PAD WIRE BOND INTERCONNECTION

WIRE BONDED WIDE I/O SEMICONDUCTOR DEVICE

NON-VOLATILE MEMORY SYSTEM WITH WIDE I/O MEMORY DIE