Gopi Ganapathy

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Simulation by emulating level sensitive latches with edge trigger l...
- Patent number 5,721,695
- Issue date Feb 24, 1998
- Advanced Micro Devices, Inc.
- Brian D. McMinn
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Simulating multi-phase clock designs using a single clock edge base...
- Patent number 5,630,100
- Issue date May 13, 1997
- Advanced Micro Devices, Inc.
- Gopi Ganapathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microprocessor with software switchable clock speed and drive strength
- Patent number 5,561,792
- Issue date Oct 1, 1996
- Advanced Micro Devices, Inc.
- Gopi Ganapathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit for delaying data latching from a precharged bus and method
- Patent number 5,502,414
- Issue date Mar 26, 1996
- Advanced Micro Devices, Inc.
- Thang Tran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pseudo master slave capture mechanism for scan elements
- Patent number 5,450,418
- Issue date Sep 12, 1995
- Advanced Micro Devices, Inc.
- Gopi Ganapathy
- G01 - MEASURING TESTING
Information Patent Grant
Microprocessor with distributed clock generators
- Patent number 5,444,407
- Issue date Aug 22, 1995
- Advanced Micro Devices, Inc.
- Gopi Ganapathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Full scan optimization technique using drive one/drive zero element...
- Patent number 5,426,650
- Issue date Jun 20, 1995
- Advanced Micro Devices, Inc.
- Gopi Ganapathy
- G01 - MEASURING TESTING
Information Patent Grant
Apparatus for synchronizing asynchronous circuits for testing opera...
- Patent number 5,412,663
- Issue date May 2, 1995
- Advanced Micro Devices, Inc.
- Stephen C. Kromer
- G01 - MEASURING TESTING

Gopi Ganapathy

Person

Patents Grantslast 30 patents

Simulation by emulating level sensitive latches with edge trigger l...

Simulating multi-phase clock designs using a single clock edge base...

Microprocessor with software switchable clock speed and drive strength

Circuit for delaying data latching from a precharged bus and method

Pseudo master slave capture mechanism for scan elements

Microprocessor with distributed clock generators

Full scan optimization technique using drive one/drive zero element...

Apparatus for synchronizing asynchronous circuits for testing opera...