Gordon J. Brebner

Person

Monte Sereno, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Network attached MPI processing architecture in smartnics
- Patent number 12,050,944
- Issue date Jul 30, 2024
- Xilinx, Inc.
- Guanwen Zhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Streaming architecture for packet parsing
- Patent number 11,831,743
- Issue date Nov 28, 2023
- Xilinx, Inc.
- Jaime Herrera
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Blockchain machine compute acceleration engine with a block verify...
- Patent number 11,743,051
- Issue date Aug 29, 2023
- Xilinx, Inc.
- Haris Javaid
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable traffic management engine
- Patent number 11,743,134
- Issue date Aug 29, 2023
- Xilinx, Inc.
- Guanwen Zhong
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Blockchain machine network acceleration engine
- Patent number 11,657,040
- Issue date May 23, 2023
- Xilinx, Inc.
- Ji Yang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable congestion control engine
- Patent number 11,641,323
- Issue date May 2, 2023
- Xilinx, Inc.
- Nguyen Duy Anh Tuan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Mining proxy acceleration
- Patent number 11,431,815
- Issue date Aug 30, 2022
- Xilinx, Inc.
- Guanwen Zhong
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Pipelined match-action circuitry
- Patent number 11,425,036
- Issue date Aug 23, 2022
- Xilinx, Inc.
- Jaime Herrera
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Programmable network measurement engine
- Patent number 11,290,361
- Issue date Mar 29, 2022
- Xilinx, Inc.
- Chengchen Hu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Streaming editor circuit for implementing a packet deparsing process
- Patent number 10,834,241
- Issue date Nov 10, 2020
- Xilinx, Inc.
- Ian McBryan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Efficient mapping of table pipelines for software-defined networkin...
- Patent number 9,674,081
- Issue date Jun 6, 2017
- Xilinx, Inc.
- Weirong Jiang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Modular and scalable cyclic redundancy check computation circuit
- Patent number 9,350,385
- Issue date May 24, 2016
- Xilinx, Inc.
- Weirong Jiang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Tuple construction from data packets
- Patent number 9,270,517
- Issue date Feb 23, 2016
- Xilinx, Inc.
- Michael E. Attig
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Embedded memory and dedicated processor structure within an integra...
- Patent number 8,874,837
- Issue date Oct 28, 2014
- Xilinx, Inc.
- Christopher E. Neely
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Parallel processing of network packets
- Patent number 8,780,914
- Issue date Jul 15, 2014
- Xilinx, Inc.
- Gordon J. Brebner
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Parallel processing of network packets
- Patent number 8,775,685
- Issue date Jul 8, 2014
- Xilinx, Inc.
- Gordon J. Brebner
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and system for preparing modularized circuit designs for dyn...
- Patent number 8,560,996
- Issue date Oct 15, 2013
- Xilinx, Inc.
- Gordon J. Brebner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pipeline of a packet processor programmed to extract packet fields
- Patent number 8,443,102
- Issue date May 14, 2013
- Xilinx, Inc.
- Michael E. Attig
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Pipeline of a packet processor programmed to concurrently perform o...
- Patent number 8,385,340
- Issue date Feb 26, 2013
- Xilinx, Inc.
- Michael E. Attig
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Generating a pipeline of a packet processor from a parsing tree
- Patent number 8,358,653
- Issue date Jan 22, 2013
- Xilinx, Inc.
- Michael E. Attig
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Managing formatting of packets of a communication protocol
- Patent number 8,311,057
- Issue date Nov 13, 2012
- Xilinx, Inc.
- Michael E. Attig
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Flexible packet data storage for diverse packet processing applicat...
- Patent number 8,266,583
- Issue date Sep 11, 2012
- Xilinx, Inc.
- Gordon J. Brebner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transforming a declarative description of a packet processor
- Patent number 8,160,092
- Issue date Apr 17, 2012
- Xilinx, Inc.
- Michael E. Attig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generation of a pipeline for processing a type of network packets
- Patent number 8,144,702
- Issue date Mar 27, 2012
- Xilinx, Inc.
- Michael E. Attig
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Graphical user interface for system design
- Patent number 8,121,826
- Issue date Feb 21, 2012
- Xilinx, Inc.
- Christopher E. Neely
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for message processing on a programmable logic device
- Patent number 8,065,130
- Issue date Nov 22, 2011
- Xilinx, Inc.
- Gordon J. Brebner
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Configurable memory manager
- Patent number 8,015,386
- Issue date Sep 6, 2011
- Xilinx, Inc.
- Chidamber R. Kulkarni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Machines for inserting or removing fixed length data at a fixed loc...
- Patent number 7,949,790
- Issue date May 24, 2011
- Xilinx, Inc.
- Philip B. James-Roxby
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Methods of clustering actions for manipulating packets of a communi...
- Patent number 7,949,007
- Issue date May 24, 2011
- Xilinx, Inc.
- Michael E. Attig
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for providing an interface between a programma...
- Patent number 7,949,793
- Issue date May 24, 2011
- Xilinx, Inc.
- Philip B. James-Roxby
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
BLOCKCHAIN MACHINE BROADCAST PROTOCOL WITH LOSS RECOVERY
- Publication number 20230370521
- Publication date Nov 16, 2023
- Xilinx, Inc.
- Ji YANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NETWORK ATTACHED MPI PROCESSING ARCHITECTURE IN SMARTNICS
- Publication number 20220358002
- Publication date Nov 10, 2022
- Xilinx, Inc.
- Guanwen ZHONG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BLOCKCHAIN MACHINE NETWORK ACCELERATION ENGINE
- Publication number 20220138178
- Publication date May 5, 2022
- Xilinx, Inc.
- Ji YANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BLOCKCHAIN MACHINE COMPUTE ACCELERATION ENGINE
- Publication number 20220131704
- Publication date Apr 28, 2022
- Xilinx, Inc.
- Haris JAVAID
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE TRAFFIC MANAGEMENT ENGINE
- Publication number 20220109613
- Publication date Apr 7, 2022
- Xilinx, Inc.
- Guanwen ZHONG
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
MODULAR AND SCALABLE CYCLIC REDUNDANCY CHECK COMPUTATION CIRCUIT
- Publication number 20140281844
- Publication date Sep 18, 2014
- Xilinx, Inc.
- Weirong Jiang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
EMBEDDED MEMORY AND DEDICATED PROCESSOR STRUCTURE WITHIN AN INTEGRA...
- Publication number 20130117504
- Publication date May 9, 2013
- Xilinx, Inc.
- Christopher E. Neely
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PARALLEL PROCESSING OF NETWORK PACKETS
- Publication number 20130094507
- Publication date Apr 18, 2013
- Xilinx, Inc.
- Gordon J. Brebner
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Gordon J. Brebner

Person

Patents Grantslast 30 patents

Network attached MPI processing architecture in smartnics

Streaming architecture for packet parsing

Blockchain machine compute acceleration engine with a block verify...

Programmable traffic management engine

Blockchain machine network acceleration engine

Programmable congestion control engine

Mining proxy acceleration

Pipelined match-action circuitry

Programmable network measurement engine

Streaming editor circuit for implementing a packet deparsing process

Efficient mapping of table pipelines for software-defined networkin...

Modular and scalable cyclic redundancy check computation circuit

Tuple construction from data packets

Embedded memory and dedicated processor structure within an integra...

Parallel processing of network packets

Parallel processing of network packets

Method and system for preparing modularized circuit designs for dyn...

Pipeline of a packet processor programmed to extract packet fields

Pipeline of a packet processor programmed to concurrently perform o...

Generating a pipeline of a packet processor from a parsing tree

Managing formatting of packets of a communication protocol

Flexible packet data storage for diverse packet processing applicat...

Transforming a declarative description of a packet processor

Generation of a pipeline for processing a type of network packets

Graphical user interface for system design

Method for message processing on a programmable logic device

Configurable memory manager

Machines for inserting or removing fixed length data at a fixed loc...

Methods of clustering actions for manipulating packets of a communi...

Method and apparatus for providing an interface between a programma...

Patents Applicationslast 30 patents

BLOCKCHAIN MACHINE BROADCAST PROTOCOL WITH LOSS RECOVERY

NETWORK ATTACHED MPI PROCESSING ARCHITECTURE IN SMARTNICS

BLOCKCHAIN MACHINE NETWORK ACCELERATION ENGINE

BLOCKCHAIN MACHINE COMPUTE ACCELERATION ENGINE

PROGRAMMABLE TRAFFIC MANAGEMENT ENGINE

MODULAR AND SCALABLE CYCLIC REDUNDANCY CHECK COMPUTATION CIRCUIT

EMBEDDED MEMORY AND DEDICATED PROCESSOR STRUCTURE WITHIN AN INTEGRA...

PARALLEL PROCESSING OF NETWORK PACKETS