Gordon W. Priebe

Person

Champlin, MN, US

People

Patents Grantslast 30 patents

Information Patent Grant
Content addressable memory continuous error detection with interlea...
- Patent number 8,924,835
- Issue date Dec 30, 2014
- LSI Corporation
- Gordon W. Priebe
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Content addressable memory data clustering block architecture
- Patent number 8,850,109
- Issue date Sep 30, 2014
- Avago Technologies General IP (Singapore) Pte. Ltd.
- David B. Grover
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Segmented memory having power-saving mode
- Patent number 8,773,942
- Issue date Jul 8, 2014
- LSI Corporation
- Richard J. Stephani
- G11 - INFORMATION STORAGE
Information Patent Grant
Low power SRAM based content addressable memory
- Patent number 8,264,862
- Issue date Sep 11, 2012
- LSI Corporation
- Richard J. Stephani
- G11 - INFORMATION STORAGE
Information Patent Grant
High speed single ended bit line sense amplifier
- Patent number 5,825,212
- Issue date Oct 20, 1998
- LSI Logic Corporation
- Gordon W. Priebe
- G11 - INFORMATION STORAGE
Information Patent Grant
High speed method and apparatus for detecting assertion of multiple...
- Patent number 5,748,070
- Issue date May 5, 1998
- LSI Logic Corporation
- Gordon W. Priebe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for detecting assertion of multiple signals
- Patent number 5,610,573
- Issue date Mar 11, 1997
- LSI Logic Corporation
- Gordon W. Priebe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast memory sense system
- Patent number 5,608,681
- Issue date Mar 4, 1997
- LSI Logic Corporation
- Gordon W. Priebe
- G11 - INFORMATION STORAGE
Information Patent Grant
Fast word line decoder for memory devices
- Patent number 5,604,712
- Issue date Feb 18, 1997
- LSI Logic Corporation
- Gordon W. Priebe
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for a low power self-timed memory control system
- Patent number 5,596,539
- Issue date Jan 21, 1997
- LSI Logic Corporation
- Robin H. Passow
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit interconnections testing
- Patent number 5,070,296
- Issue date Dec 3, 1991
- Honeywell Inc.
- Gordon W. Priebe
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
SEGMENTED MEMORY HAVING POWER-SAVING MODE
- Publication number 20140119147
- Publication date May 1, 2014
- LSI Corporation
- Richard J. Stephani
- G11 - INFORMATION STORAGE
Information Patent Application
CONTENT ADDRESSABLE MEMORY CONTINUOUS ERROR DETECTION WITH INTERLEA...
- Publication number 20140089769
- Publication date Mar 27, 2014
- LSI Corporation
- Gordon W. Priebe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTENT ADDRESSABLE MEMORY DATA CLUSTERING BLOCK ARCHITECTURE
- Publication number 20130166850
- Publication date Jun 27, 2013
- David B. Grover
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW POWER SRAM BASED CONTENT ADDRESSABLE MEMORY
- Publication number 20120127772
- Publication date May 24, 2012
- Richard J. Stephani
- G11 - INFORMATION STORAGE

Gordon W. Priebe

Person

Patents Grantslast 30 patents

Content addressable memory continuous error detection with interlea...

Content addressable memory data clustering block architecture

Segmented memory having power-saving mode

Low power SRAM based content addressable memory

High speed single ended bit line sense amplifier

High speed method and apparatus for detecting assertion of multiple...

Method and apparatus for detecting assertion of multiple signals

Fast memory sense system

Fast word line decoder for memory devices

Method and apparatus for a low power self-timed memory control system

Integrated circuit interconnections testing

Patents Applicationslast 30 patents

SEGMENTED MEMORY HAVING POWER-SAVING MODE

CONTENT ADDRESSABLE MEMORY CONTINUOUS ERROR DETECTION WITH INTERLEA...

CONTENT ADDRESSABLE MEMORY DATA CLUSTERING BLOCK ARCHITECTURE

LOW POWER SRAM BASED CONTENT ADDRESSABLE MEMORY