Grant Lindberg

Person

Pleasanton, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
I/O planning with lock and insertion features
- Patent number 8,099,708
- Issue date Jan 17, 2012
- LSI Corporation
- Grant Lindberg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
I/O planning with lock and insertion features
- Patent number 7,543,261
- Issue date Jun 2, 2009
- LSI Corporation
- Grant Lindberg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
IP placement validation
- Patent number 7,469,398
- Issue date Dec 23, 2008
- LSI Corporation
- Gregor J. Martin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Resource estimation for design planning
- Patent number 7,464,345
- Issue date Dec 9, 2008
- LSI Corporation
- Gregor J. Martin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enabling efficient design reuse in platform ASICs
- Patent number 7,299,446
- Issue date Nov 20, 2007
- LSI Corporation
- Ying Chun He
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Guided capture, creation, and seamless integration with scalable co...
- Patent number 7,290,224
- Issue date Oct 30, 2007
- LSI Corporation
- Jonathan Byrn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Floorplan visualization method using gate count and gate density es...
- Patent number 7,197,735
- Issue date Mar 27, 2007
- LSI Logic Corporation
- Gregor J. Martin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay/load estimation for use in integrated circuit design
- Patent number 6,634,014
- Issue date Oct 14, 2003
- LSI Logic Corporation
- Grant Lindberg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Defect isolation using scan-path testing and electron beam probing...
- Patent number 5,663,967
- Issue date Sep 2, 1997
- LSI Logic Corporation
- Grant A. Lindberg
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
I/O PLANNING WITH LOCK AND INSERTION FEATURES
- Publication number 20090210846
- Publication date Aug 20, 2009
- Grant Lindberg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IP placement validation
- Publication number 20070044059
- Publication date Feb 22, 2007
- LSI Logic Corporation
- Gregor J. Martin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Enabling efficient design reuse in platform ASICs
- Publication number 20070044058
- Publication date Feb 22, 2007
- LSI Logic Corporation
- Ying Chun He
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Resource estimation for design planning
- Publication number 20070028196
- Publication date Feb 1, 2007
- LSI Logic Corporation
- Gregor J. Martin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
I /O planning with lock and insertion features
- Publication number 20060248491
- Publication date Nov 2, 2006
- LSI Logic Corporation
- Grant Lindberg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Floorplan visualization method
- Publication number 20060129963
- Publication date Jun 15, 2006
- LSI Logic Corporation
- Gregor J. Martin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Guided capture, creation, and seamless integration with scalable co...
- Publication number 20050273738
- Publication date Dec 8, 2005
- LSI Logic Corporation
- Jonathan Byrn
- G06 - COMPUTING CALCULATING COUNTING

Grant Lindberg

Person

Patents Grantslast 30 patents

I/O planning with lock and insertion features

I/O planning with lock and insertion features

IP placement validation

Resource estimation for design planning

Enabling efficient design reuse in platform ASICs

Guided capture, creation, and seamless integration with scalable co...

Floorplan visualization method using gate count and gate density es...

Delay/load estimation for use in integrated circuit design

Defect isolation using scan-path testing and electron beam probing...

Patents Applicationslast 30 patents

I/O PLANNING WITH LOCK AND INSERTION FEATURES

IP placement validation

Enabling efficient design reuse in platform ASICs

Resource estimation for design planning

I /O planning with lock and insertion features

Floorplan visualization method

Guided capture, creation, and seamless integration with scalable co...