Greg C. Baldwin

Person

Plano, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Transistor with quantum point contact
- Patent number 10,079,286
- Issue date Sep 18, 2018
- Texas Instruments Incorporated
- Henry Litzmann Edwards
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods and apparatus for artificial exciton in CMOS processes
- Patent number 10,068,903
- Issue date Sep 4, 2018
- Texas Instruments Incorporated
- Henry Litzmann Edwards
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit with dual stress liner boundary
- Patent number 9,953,967
- Issue date Apr 24, 2018
- Texas Instruments Incorporated
- Youn Sung Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dummy gate placement methodology to enhance integrated circuit perf...
- Patent number 9,947,765
- Issue date Apr 17, 2018
- Texas Instruments Incorporated
- Younsung Choi
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Optimized layout for relaxed and strained liner in single stress li...
- Patent number 9,735,159
- Issue date Aug 15, 2017
- Texas Instruments Incorporated
- Younsung Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods and apparatus for quantum point contacts in CMOS processes
- Patent number 9,659,934
- Issue date May 23, 2017
- Texas Instruments Incorporated
- Henry Litzmann Edwards
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit with dual stress liner boundary
- Patent number 9,543,437
- Issue date Jan 10, 2017
- Texas Instruments Incorporated
- Youn Sung Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low temperature coefficient resistor in CMOS flow
- Patent number 9,543,374
- Issue date Jan 10, 2017
- Texas Instruments Incorporated
- Greg Charles Baldwin
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Dummy gate placement methodology to enhance integrated circuit perf...
- Patent number 9,496,142
- Issue date Nov 15, 2016
- Texas Instruments Incorporated
- Younsung Choi
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method for improving device performance using dual stress liner bou...
- Patent number 9,171,901
- Issue date Oct 27, 2015
- Texas Instruments Incorporated
- Youn Sung Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methodology of forming CMOS gates on the secondary axis using doubl...
- Patent number 9,054,214
- Issue date Jun 9, 2015
- Texas Instruments Incorporated
- Gregory Charles Baldwin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low temperature coefficient resistor in CMOS flow
- Patent number 8,940,598
- Issue date Jan 27, 2015
- Texas Instruments Incorporated
- Greg Charles Baldwin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for improving device performance using dual stress liner bou...
- Patent number 8,859,357
- Issue date Oct 14, 2014
- Texas Instruments Incorporated
- Youn Sung Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device layout in integrated circuits to reduce stress from embedded...
- Patent number 8,791,527
- Issue date Jul 29, 2014
- Texas Instruments Incorporated
- Gregory Charles Baldwin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit having silicide block resistor
- Patent number 8,748,256
- Issue date Jun 10, 2014
- Texas Instruments Incorporated
- Song Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Scribe line test modules for in-line monitoring of context dependen...
- Patent number 8,669,775
- Issue date Mar 11, 2014
- Texas Instruments Incorporated
- Youn Sung Choi
- G01 - MEASURING TESTING
Information Patent Grant
On-die parametric test modules for in-line monitoring of context de...
- Patent number 8,664,968
- Issue date Mar 4, 2014
- Texas Instruments Incorporated
- Gregory Charles Baldwin
- G01 - MEASURING TESTING
Information Patent Grant
Method of building compensated isolated P-well devices
- Patent number 8,609,483
- Issue date Dec 17, 2013
- Texas Instruments Incorporated
- Kamel Benaissa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Compensated isolated p-well DENMOS devices
- Patent number 8,604,543
- Issue date Dec 10, 2013
- Texas Instruments Incorporated
- Kamel Benaissa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Marker layer to facilitate mask build with interactive layers
- Patent number 8,595,656
- Issue date Nov 26, 2013
- Texas Instruments Incorporated
- Thomas J. Aton
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Flexible integration of logic blocks with transistors of different...
- Patent number 8,513,105
- Issue date Aug 20, 2013
- Texas Instruments Incorporated
- Gregory Charles Baldwin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for minimizing transistor and analog component variation in...
- Patent number 8,438,526
- Issue date May 7, 2013
- Texas Instruments Incorporated
- Gregory Charles Baldwin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low cost transistors using gate orientation and optimized implants
- Patent number 8,405,154
- Issue date Mar 26, 2013
- Texas Instruments Incorporated
- Kamel Benaissa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS integration method for optimal IO transistor VT
- Patent number 8,377,772
- Issue date Feb 19, 2013
- Texas Instruments Incorporated
- Weize Xiong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit inductor with integrated vias
- Patent number 8,344,479
- Issue date Jan 1, 2013
- Texas Instruments Incorporated
- Robert L. Pitts
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Compensated isolated p-well DENMOS devices
- Patent number 8,232,158
- Issue date Jul 31, 2012
- Texas Instruments Incorporated
- Kamel Benaissa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device layout in integrated circuits to reduce stress from embedded...
- Patent number 8,183,117
- Issue date May 22, 2012
- Texas Instruments Incorporated
- Gregory Charles Baldwin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Differential poly doping and circuits therefrom
- Patent number 8,114,729
- Issue date Feb 14, 2012
- Texas Instruments Incorporated
- Shashank Ekbote
- G11 - INFORMATION STORAGE
Information Patent Grant
Low cost transistors using gate orientation and optimized implants
- Patent number 7,994,009
- Issue date Aug 9, 2011
- Kamel Benaissa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit inductor with integrated vias
- Patent number 7,888,227
- Issue date Feb 15, 2011
- Texas Instruments Incorporated
- Robert L. Pitts
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
TRANSISTOR WITH QUANTUM POINT CONTACT
- Publication number 20170200796
- Publication date Jul 13, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Henry Litzmann Edwards
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT WITH DUAL STRESS LINER BOUNDARY
- Publication number 20170084598
- Publication date Mar 23, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Youn Sung Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUMMY GATE PLACEMENT METHODOLOGY TO ENHANCE INTEGRATED CIRCUIT PERF...
- Publication number 20170062582
- Publication date Mar 2, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Younsung CHOI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT WITH DUAL STRESS LINER BOUNDARY
- Publication number 20160013314
- Publication date Jan 14, 2016
- TEXAS INSTRUMENTS INCORPORATED
- Youn Sung Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods and Apparatus for Artificial Exciton in CMOS Processes
- Publication number 20150348968
- Publication date Dec 3, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Henry Litzmann Edwards
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods and Apparatus for Quantum Point Contacts in CMOS Processes
- Publication number 20150348969
- Publication date Dec 3, 2015
- TEXAS INSTRUMENTS INCORPORATION
- Henry Litzmann Edwards
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
OPTIMIZED LAYOUT FOR RELAXED AND STRAINED LINER IN SINGLE STRESS LI...
- Publication number 20150187772
- Publication date Jul 2, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Younsung CHOI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUMMY GATE PLACEMENT METHODOLOGY TO ENHANCE INTEGRATED CIRCUIT PERF...
- Publication number 20150187585
- Publication date Jul 2, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Younsung CHOI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODOLOGY OF FORMING CMOS GATES ON THE SECONDARY AXIS USING DOUBL...
- Publication number 20150170971
- Publication date Jun 18, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Gregory Charles BALDWIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW TEMPERATURE COEFFICIENT RESISTOR IN CMOS FLOW
- Publication number 20150171158
- Publication date Jun 18, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Greg Charles BALDWIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR IMPROVING DEVICE PERFORMANCE USING DUAL STRESS LINER BOU...
- Publication number 20140374836
- Publication date Dec 25, 2014
- Youn Sung CHOI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT HAVING SILICIDE BLOCK RESISTOR
- Publication number 20130200466
- Publication date Aug 8, 2013
- TEXAS INSTRUMENTS INCORPORATED
- SONG ZHAO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SRAM STRUCTURE AND PROCESS WITH IMPROVED STABILITY
- Publication number 20120280324
- Publication date Nov 8, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Weize Xiong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Compensated Isolated P-WELL DENMOS Devices
- Publication number 20120261766
- Publication date Oct 18, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Kamel Benaissa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE LAYOUT IN INTEGRATED CIRCUITS TO REDUCE STRESS FROM EMBEDDED...
- Publication number 20120205748
- Publication date Aug 16, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Gregory Charles Baldwin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR IMPROVING DEVICE PERFORMANCE USING DUAL STRESS LINER BOU...
- Publication number 20120119301
- Publication date May 17, 2012
- Texas Instrument Incorporated
- Youn Sung Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW TEMPERATURE COEFFICIENT RESISTOR IN CMOS FLOW
- Publication number 20120108020
- Publication date May 3, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Greg Charles BALDWIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MARKER LAYER TO FACILITATE MASK BUILD WITH INTERACTIVE LAYERS
- Publication number 20120102441
- Publication date Apr 26, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Thomas J. Aton
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Flexible Integration of Logic Blocks with Transistors of Different...
- Publication number 20120091531
- Publication date Apr 19, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Gregory Charles Baldwin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SCRIBE LINE TEST MODULES FOR IN-LINE MONITORING OF CONTEXT DEPENDEN...
- Publication number 20120074980
- Publication date Mar 29, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Youn Sung Choi
- G01 - MEASURING TESTING
Information Patent Application
METHOD FOR MINIMIZING TRANSISTOR AND ANALOG COMPONENT VARIATION IN...
- Publication number 20120078604
- Publication date Mar 29, 2012
- Gregory Charles Baldwin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ON-DIE PARAMETRIC TEST MODULES FOR IN-LINE MONITORING OF CONTEXT DE...
- Publication number 20120074973
- Publication date Mar 29, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Gregory Charles Baldwin
- G01 - MEASURING TESTING
Information Patent Application
Device Layout in Integrated Circuits to Reduce Stress from Embedded...
- Publication number 20120043612
- Publication date Feb 23, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Gregory Charles Baldwin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMOS INTEGRATION METHOD FOR OPTIMAL IO TRANSISTOR VT
- Publication number 20120045874
- Publication date Feb 23, 2012
- Weize XIONG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW COST TRANSISTORS USING GATE ORIENTATION AND OPTIMIZED IMPLANTS
- Publication number 20110248347
- Publication date Oct 13, 2011
- TEXAS INSTRUMENTS INCORPORATED
- Kamel BENAISSA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Compensated Isolated P-WELL DENMOS Devices
- Publication number 20110156144
- Publication date Jun 30, 2011
- TEXAS INSTRUMENTS INCORPORATED
- Kamel Benaissa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT INDUCTOR WITH INTEGRATED VIAS
- Publication number 20110133880
- Publication date Jun 9, 2011
- TEXAS INSTRUMENTS INCORPORATED
- Robert L. Pitts
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW COST TRANSISTORS USING GATE ORIENTATION AND OPTIMIZED IMPLANTS
- Publication number 20100327374
- Publication date Dec 30, 2010
- Kamel Benaissa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF BUILDING COMPENSATED ISOLATED P-WELL DEVICES
- Publication number 20100327335
- Publication date Dec 30, 2010
- TEXAS INSTRUMENTS INCORPORATED
- Kamel BENAISSA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW COST SYMMETRIC TRANSISTORS
- Publication number 20100327361
- Publication date Dec 30, 2010
- KAMEL BENAISSA
- H01 - BASIC ELECTRIC ELEMENTS

Greg C. Baldwin

Person

Patents Grantslast 30 patents

Transistor with quantum point contact

Methods and apparatus for artificial exciton in CMOS processes

Integrated circuit with dual stress liner boundary

Dummy gate placement methodology to enhance integrated circuit perf...

Optimized layout for relaxed and strained liner in single stress li...

Methods and apparatus for quantum point contacts in CMOS processes

Integrated circuit with dual stress liner boundary

Low temperature coefficient resistor in CMOS flow

Dummy gate placement methodology to enhance integrated circuit perf...

Method for improving device performance using dual stress liner bou...

Methodology of forming CMOS gates on the secondary axis using doubl...

Low temperature coefficient resistor in CMOS flow

Method for improving device performance using dual stress liner bou...

Device layout in integrated circuits to reduce stress from embedded...

Integrated circuit having silicide block resistor

Scribe line test modules for in-line monitoring of context dependen...

On-die parametric test modules for in-line monitoring of context de...

Method of building compensated isolated P-well devices

Compensated isolated p-well DENMOS devices

Marker layer to facilitate mask build with interactive layers

Flexible integration of logic blocks with transistors of different...

Method for minimizing transistor and analog component variation in...

Low cost transistors using gate orientation and optimized implants

CMOS integration method for optimal IO transistor VT

Integrated circuit inductor with integrated vias

Compensated isolated p-well DENMOS devices

Device layout in integrated circuits to reduce stress from embedded...

Differential poly doping and circuits therefrom

Low cost transistors using gate orientation and optimized implants

Integrated circuit inductor with integrated vias

Patents Applicationslast 30 patents

TRANSISTOR WITH QUANTUM POINT CONTACT

INTEGRATED CIRCUIT WITH DUAL STRESS LINER BOUNDARY

DUMMY GATE PLACEMENT METHODOLOGY TO ENHANCE INTEGRATED CIRCUIT PERF...

INTEGRATED CIRCUIT WITH DUAL STRESS LINER BOUNDARY

Methods and Apparatus for Artificial Exciton in CMOS Processes

Methods and Apparatus for Quantum Point Contacts in CMOS Processes

OPTIMIZED LAYOUT FOR RELAXED AND STRAINED LINER IN SINGLE STRESS LI...

DUMMY GATE PLACEMENT METHODOLOGY TO ENHANCE INTEGRATED CIRCUIT PERF...

METHODOLOGY OF FORMING CMOS GATES ON THE SECONDARY AXIS USING DOUBL...

LOW TEMPERATURE COEFFICIENT RESISTOR IN CMOS FLOW

METHOD FOR IMPROVING DEVICE PERFORMANCE USING DUAL STRESS LINER BOU...

INTEGRATED CIRCUIT HAVING SILICIDE BLOCK RESISTOR

SRAM STRUCTURE AND PROCESS WITH IMPROVED STABILITY

Compensated Isolated P-WELL DENMOS Devices

DEVICE LAYOUT IN INTEGRATED CIRCUITS TO REDUCE STRESS FROM EMBEDDED...

METHOD FOR IMPROVING DEVICE PERFORMANCE USING DUAL STRESS LINER BOU...

LOW TEMPERATURE COEFFICIENT RESISTOR IN CMOS FLOW

MARKER LAYER TO FACILITATE MASK BUILD WITH INTERACTIVE LAYERS

Flexible Integration of Logic Blocks with Transistors of Different...

SCRIBE LINE TEST MODULES FOR IN-LINE MONITORING OF CONTEXT DEPENDEN...

METHOD FOR MINIMIZING TRANSISTOR AND ANALOG COMPONENT VARIATION IN...

ON-DIE PARAMETRIC TEST MODULES FOR IN-LINE MONITORING OF CONTEXT DE...

Device Layout in Integrated Circuits to Reduce Stress from Embedded...

CMOS INTEGRATION METHOD FOR OPTIMAL IO TRANSISTOR VT

LOW COST TRANSISTORS USING GATE ORIENTATION AND OPTIMIZED IMPLANTS

Compensated Isolated P-WELL DENMOS Devices

INTEGRATED CIRCUIT INDUCTOR WITH INTEGRATED VIAS

LOW COST TRANSISTORS USING GATE ORIENTATION AND OPTIMIZED IMPLANTS

METHOD OF BUILDING COMPENSATED ISOLATED P-WELL DEVICES

LOW COST SYMMETRIC TRANSISTORS