Greg P. Shaurette

Person

Tahoe City, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Systems and methods for obfuscating a circuit design
- Patent number 11,775,722
- Issue date Oct 3, 2023
- efabless corporation
- Bertrand Irissou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for engineering integrated circuit design and development
- Patent number 11,748,541
- Issue date Sep 5, 2023
- efabless corporation
- Bertrand Irissou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for obfuscating a circuit design
- Patent number 11,301,609
- Issue date Apr 12, 2022
- efabless corporation
- Bertrand Irissou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for engineering integrated circuit design and development
- Patent number 11,182,526
- Issue date Nov 23, 2021
- efabless corporation
- Bertrand Irissou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for obfuscating a circuit design
- Patent number 10,671,700
- Issue date Jun 2, 2020
- efavless corporation
- Bertrand Irissou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for engineering integrated circuit design and development
- Patent number 10,452,802
- Issue date Oct 22, 2019
- efabless corporation
- Bertrand Irissou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems for engineering integrated circuit design and development
- Patent number 10,437,953
- Issue date Oct 8, 2019
- efabless corporation
- Bertrand Irissou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for obfuscating a circuit design
- Patent number 10,423,748
- Issue date Sep 24, 2019
- efabless corporation
- Bertrand Irissou
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SYSTEMS AND METHODS FOR OBFUSCATING A CIRCUIT DESIGN
- Publication number 20220277126
- Publication date Sep 1, 2022
- efabless corporation
- Bertrand Irissou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS FOR ENGINEERING INTEGRATED CIRCUIT DESIGN AND DEVELOPMENT
- Publication number 20220043956
- Publication date Feb 10, 2022
- efabless corporation
- Bertrand Irissou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR OBFUSCATING A CIRCUIT DESIGN
- Publication number 20220027544
- Publication date Jan 27, 2022
- efabless corporation
- Bertrand Irissou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR OBFUSCATING A CIRCUIT DESIGN
- Publication number 20200285795
- Publication date Sep 10, 2020
- efabless corporation
- Bertrand Irissou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS FOR ENGINEERING INTEGRATED CIRCUIT DESIGN AND DEVELOPMENT
- Publication number 20200089833
- Publication date Mar 19, 2020
- efabless corporation
- Bertrand Irissou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR OBFUSCATING A CIRCUIT DESIGN
- Publication number 20190392105
- Publication date Dec 26, 2019
- efabless corporation
- Bertrand Irissou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR OBFUSCATING A CIRCUIT DESIGN
- Publication number 20180011959
- Publication date Jan 11, 2018
- efabless corporation
- Bertrand Irissou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS FOR ENGINEERING INTEGRATED CIRCUIT DESIGN AND DEVELOPMENT
- Publication number 20180011948
- Publication date Jan 11, 2018
- efabless corporation
- Bertrand Irissou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS FOR ENGINEERING INTEGRATED CIRCUIT DESIGN AND DEVELOPMENT
- Publication number 20180011958
- Publication date Jan 11, 2018
- efabless corporation
- Bertrand Irissou
- G06 - COMPUTING CALCULATING COUNTING

Greg P. Shaurette

Person

Patents Grantslast 30 patents

Systems and methods for obfuscating a circuit design

Methods for engineering integrated circuit design and development

Systems and methods for obfuscating a circuit design

Methods for engineering integrated circuit design and development

Systems and methods for obfuscating a circuit design

Methods for engineering integrated circuit design and development

Systems for engineering integrated circuit design and development

Systems and methods for obfuscating a circuit design

Patents Applicationslast 30 patents

SYSTEMS AND METHODS FOR OBFUSCATING A CIRCUIT DESIGN

METHODS FOR ENGINEERING INTEGRATED CIRCUIT DESIGN AND DEVELOPMENT

SYSTEMS AND METHODS FOR OBFUSCATING A CIRCUIT DESIGN

SYSTEMS AND METHODS FOR OBFUSCATING A CIRCUIT DESIGN

METHODS FOR ENGINEERING INTEGRATED CIRCUIT DESIGN AND DEVELOPMENT

SYSTEMS AND METHODS FOR OBFUSCATING A CIRCUIT DESIGN

SYSTEMS AND METHODS FOR OBFUSCATING A CIRCUIT DESIGN

SYSTEMS FOR ENGINEERING INTEGRATED CIRCUIT DESIGN AND DEVELOPMENT

METHODS FOR ENGINEERING INTEGRATED CIRCUIT DESIGN AND DEVELOPMENT