Gregg William Baeckler

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Programmable integrated circuit underlay
- Patent number 12,086,518
- Issue date Sep 10, 2024
- Intel Corporation
- Gregg William Baeckler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic device with fine-grained disaggregation
- Patent number 11,595,045
- Issue date Feb 28, 2023
- Intel Corporation
- Dheeraj Subbareddy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High performance regularized network-on-chip architecture
- Patent number 11,556,692
- Issue date Jan 17, 2023
- Intel Corporation
- Gregg William Baeckler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Geometric synthesis
- Patent number 11,467,804
- Issue date Oct 11, 2022
- Intel Corporation
- Sergey Vladimirovich Gribok
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing multiplier regularization
- Patent number 11,436,399
- Issue date Sep 6, 2022
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Deterministic clustering and packing method for random logic on pro...
- Patent number 11,301,611
- Issue date Apr 12, 2022
- Intel Corporation
- Gregg William Baeckler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuitry for low-precision deep learning
- Patent number 11,275,998
- Issue date Mar 15, 2022
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing field programmable gate array p...
- Patent number 11,216,249
- Issue date Jan 4, 2022
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Machine learning training architecture for programmable devices
- Patent number 11,210,063
- Issue date Dec 28, 2021
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable-logic-directed multiplier mapping
- Patent number 11,163,530
- Issue date Nov 2, 2021
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing synthesis for field programmabl...
- Patent number 11,080,019
- Issue date Aug 3, 2021
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic device with fine-grained disaggregation
- Patent number 11,070,209
- Issue date Jul 20, 2021
- Intel Corporation
- Dheeraj Subbareddy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Continuous carry-chain packing
- Patent number 11,016,733
- Issue date May 25, 2021
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High radix subset code multiplier architecture
- Patent number 11,010,134
- Issue date May 18, 2021
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reduction operation mapping systems and methods
- Patent number 11,003,446
- Issue date May 11, 2021
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance regularized network-on-chip architecture
- Patent number 10,922,471
- Issue date Feb 16, 2021
- Intel Corporation
- Gregg William Baeckler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for using a multiplier to support multiple sub-multiplicati...
- Patent number 10,871,946
- Issue date Dec 22, 2020
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for implementing an application aware system o...
- Patent number 10,867,090
- Issue date Dec 15, 2020
- Intel Corporation
- Gregg William Baeckler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic circuits with simultaneous dual function capability
- Patent number 10,790,829
- Issue date Sep 29, 2020
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for using a multiplier circuit to support multiple sub-mult...
- Patent number 10,732,932
- Issue date Aug 4, 2020
- Intel Corporation
- Bogdan Pasca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic circuits with augmented arithmetic densities
- Patent number 10,715,144
- Issue date Jul 14, 2020
- Intel Corporation
- Sergey Gribok
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic device with fine-grained disaggregation
- Patent number 10,601,426
- Issue date Mar 24, 2020
- Intel Corporation
- Dheeraj Subbareddy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Scalable circuitry and method for control insertion
- Patent number 10,296,479
- Issue date May 21, 2019
- Altera Corporation
- Gregg William Baeckler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Omnibus logic element
- Patent number 10,177,766
- Issue date Jan 8, 2019
- Altera Corporation
- James Schleicher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for improving a design for a system during com...
- Patent number 10,162,919
- Issue date Dec 25, 2018
- Altera Corporation
- Gregg William Baeckler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Move based XOR optimization
- Patent number 10,073,940
- Issue date Sep 11, 2018
- Altera Corporation
- Gregg William Baeckler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed burst error protection
- Patent number 9,941,903
- Issue date Apr 10, 2018
- Altera Corporation
- David W. Mendel
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus for improved communication and associated methods
- Patent number 9,544,092
- Issue date Jan 10, 2017
- Altera Corporation
- Gregg William Baeckler
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Omnibus logic element
- Patent number 9,496,875
- Issue date Nov 15, 2016
- Altera Corporation
- James Schleicher
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus for improved encoding and associated methods
- Patent number 9,490,836
- Issue date Nov 8, 2016
- Altera Corporation
- David Mendel
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
PROGRAMMABLE INTEGRATED CIRCUIT UNDERLAY
- Publication number 20240394448
- Publication date Nov 28, 2024
- Intel Corporation
- Gregg William Baeckler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Fast CAD Compilation Through Coarse Macro Lowering
- Publication number 20240020449
- Publication date Jan 18, 2024
- Intel Corporation
- Byron Sinclair
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Pipelined Galois Counter Mode Hash Circuit
- Publication number 20230239136
- Publication date Jul 27, 2023
- Sergey Vladimirovich Gribok
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Systems And Methods For Correcting Errors in Code For Circuit Designs
- Publication number 20230222275
- Publication date Jul 13, 2023
- Intel Corporation
- Gregg Baeckler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE LOGIC DEVICE WITH FINE-GRAINED DISAGGREGATION
- Publication number 20230198526
- Publication date Jun 22, 2023
- Intel Corporation
- Dheeraj Subbareddy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Techniques For Compiling High-Level Inline Code
- Publication number 20230116554
- Publication date Apr 13, 2023
- Intel Corporation
- Gregg Baeckler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Power Savings by Register Insertion in Large Combinational Circuits
- Publication number 20230027064
- Publication date Jan 26, 2023
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Retiming and Overclocking of Large Circuits
- Publication number 20230018414
- Publication date Jan 19, 2023
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MACHINE LEARNING TRAINING ARCHITECTURE FOR PROGRAMMABLE DEVICES
- Publication number 20220107783
- Publication date Apr 7, 2022
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE LOGIC DEVICE WITH FINE-GRAINED DISAGGREGATION
- Publication number 20210328589
- Publication date Oct 21, 2021
- Intel Corporation
- Dheeraj Subbareddy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Vector Processor Architectures
- Publication number 20210216318
- Publication date Jul 15, 2021
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
High Performance Regularized Network-on-Chip Architecture
- Publication number 20210117607
- Publication date Apr 22, 2021
- Intel Corporation
- Gregg William Baeckler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE INTEGRATED CIRCUIT UNDERLAY
- Publication number 20200293707
- Publication date Sep 17, 2020
- Intel Corporation
- Gregg William Baeckler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Hazard Mitigation for Lightweight Processor Cores
- Publication number 20200278865
- Publication date Sep 3, 2020
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE LOGIC DEVICE WITH FINE-GRAINED DISAGGREGATION
- Publication number 20200186149
- Publication date Jun 11, 2020
- Intel Corporation
- Dheeraj Subbareddy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHODS FOR USING A MULTIPLIER CIRCUIT TO SUPPORT MULTIPLE SUB-MULT...
- Publication number 20200142671
- Publication date May 7, 2020
- Intel Corporation
- Bogdan Pasca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DETERMINISTIC CLUSTERING AND PACKING METHOD FOR RANDOM LOGIC ON PRO...
- Publication number 20200125780
- Publication date Apr 23, 2020
- Intel Corporation
- Gregg William Baeckler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOGIC CIRCUITS WITH SIMULTANEOUS DUAL FUNCTION CAPABILITY
- Publication number 20200106442
- Publication date Apr 2, 2020
- Intel Corporation
- Martin LANGHAMMER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE LOGIC DEVICE WITH FINE-GRAINED DISAGGREGATION
- Publication number 20200083890
- Publication date Mar 12, 2020
- Intel Corporation
- Dheeraj Subbareddy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MACHINE LEARNING TRAINING ARCHITECTURE FOR PROGRAMMABLE DEVICES
- Publication number 20200026494
- Publication date Jan 23, 2020
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Geometric Synthesis
- Publication number 20190324724
- Publication date Oct 24, 2019
- Sergey Vladimirovich Gribok
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
High Performance Regularized Network-on-Chip Architecture
- Publication number 20190318058
- Publication date Oct 17, 2019
- Gregg William Baeckler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOGIC CIRCUITS WITH AUGMENTED ARITHMETIC DENSITIES
- Publication number 20190288688
- Publication date Sep 19, 2019
- Intel Corporation
- Sergey Gribok
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR IMPLEMENTING AN APPLICATION AWARE SYSTEM O...
- Publication number 20190213289
- Publication date Jul 11, 2019
- Intel Corporation
- Gregg William BAECKLER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR PERFORMING MULTIPLIER REGULARIZATION
- Publication number 20190121927
- Publication date Apr 25, 2019
- Intel Corporation
- Martin LANGHAMMER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Continuous Carry-Chain Packing
- Publication number 20190042200
- Publication date Feb 7, 2019
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR PERFORMING FIELD PROGRAMMABLE GATE ARRAY P...
- Publication number 20190042674
- Publication date Feb 7, 2019
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUITRY FOR LOW-PRECISION DEEP LEARNING
- Publication number 20190042939
- Publication date Feb 7, 2019
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR PERFORMING SYNTHESIS FOR FIELD PROGRAMMABL...
- Publication number 20190042683
- Publication date Feb 7, 2019
- Intel Corporation
- Martin LANGHAMMER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programmable-Logic-Directed Multiplier Mapping
- Publication number 20190042197
- Publication date Feb 7, 2019
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING

Gregg William Baeckler

Person

Patents Grantslast 30 patents

Programmable integrated circuit underlay

Programmable logic device with fine-grained disaggregation

High performance regularized network-on-chip architecture

Geometric synthesis

Method and apparatus for performing multiplier regularization

Deterministic clustering and packing method for random logic on pro...

Circuitry for low-precision deep learning

Method and apparatus for performing field programmable gate array p...

Machine learning training architecture for programmable devices

Programmable-logic-directed multiplier mapping

Method and apparatus for performing synthesis for field programmabl...

Programmable logic device with fine-grained disaggregation

Continuous carry-chain packing

High radix subset code multiplier architecture

Reduction operation mapping systems and methods

High performance regularized network-on-chip architecture

Methods for using a multiplier to support multiple sub-multiplicati...

Method and apparatus for implementing an application aware system o...

Logic circuits with simultaneous dual function capability

Methods for using a multiplier circuit to support multiple sub-mult...

Logic circuits with augmented arithmetic densities

Programmable logic device with fine-grained disaggregation

Scalable circuitry and method for control insertion

Omnibus logic element

Method and apparatus for improving a design for a system during com...

Move based XOR optimization

Distributed burst error protection

Apparatus for improved communication and associated methods

Omnibus logic element

Apparatus for improved encoding and associated methods

Patents Applicationslast 30 patents

PROGRAMMABLE INTEGRATED CIRCUIT UNDERLAY

Fast CAD Compilation Through Coarse Macro Lowering

Pipelined Galois Counter Mode Hash Circuit

Systems And Methods For Correcting Errors in Code For Circuit Designs

PROGRAMMABLE LOGIC DEVICE WITH FINE-GRAINED DISAGGREGATION

Techniques For Compiling High-Level Inline Code

Power Savings by Register Insertion in Large Combinational Circuits

Retiming and Overclocking of Large Circuits

MACHINE LEARNING TRAINING ARCHITECTURE FOR PROGRAMMABLE DEVICES

PROGRAMMABLE LOGIC DEVICE WITH FINE-GRAINED DISAGGREGATION

Vector Processor Architectures

High Performance Regularized Network-on-Chip Architecture

PROGRAMMABLE INTEGRATED CIRCUIT UNDERLAY

Hazard Mitigation for Lightweight Processor Cores

PROGRAMMABLE LOGIC DEVICE WITH FINE-GRAINED DISAGGREGATION

METHODS FOR USING A MULTIPLIER CIRCUIT TO SUPPORT MULTIPLE SUB-MULT...

DETERMINISTIC CLUSTERING AND PACKING METHOD FOR RANDOM LOGIC ON PRO...

LOGIC CIRCUITS WITH SIMULTANEOUS DUAL FUNCTION CAPABILITY

PROGRAMMABLE LOGIC DEVICE WITH FINE-GRAINED DISAGGREGATION

MACHINE LEARNING TRAINING ARCHITECTURE FOR PROGRAMMABLE DEVICES

Geometric Synthesis

High Performance Regularized Network-on-Chip Architecture

LOGIC CIRCUITS WITH AUGMENTED ARITHMETIC DENSITIES

METHOD AND APPARATUS FOR IMPLEMENTING AN APPLICATION AWARE SYSTEM O...

METHOD AND APPARATUS FOR PERFORMING MULTIPLIER REGULARIZATION

Continuous Carry-Chain Packing

METHOD AND APPARATUS FOR PERFORMING FIELD PROGRAMMABLE GATE ARRAY P...

CIRCUITRY FOR LOW-PRECISION DEEP LEARNING

METHOD AND APPARATUS FOR PERFORMING SYNTHESIS FOR FIELD PROGRAMMABL...

Programmable-Logic-Directed Multiplier Mapping