Membership
Tour
Register
Log in
Gregory S. Mathews
Follow
Person
Saratoga, CA, US
People
Overview
Industries
Organizations
People
Information
Impact
Patents Grants
last 30 patents
Information
Patent Grant
Priority-biased exit queue arbitration with fairness
Patent number
8,090,869
Issue date
Jan 3, 2012
Alcatel Lucent
Greg Mathews
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information
Patent Grant
Testing and error recovery across multiple switching fabrics
Patent number
7,876,693
Issue date
Jan 25, 2011
Alcatel-Lucent USA Inc.
Gregory S. Mathews
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information
Patent Grant
Hierarchical rate limiting with proportional limiting
Patent number
7,801,045
Issue date
Sep 21, 2010
Alcatel Lucent
Gregory S. Mathews
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information
Patent Grant
Pointer allocation by prime numbers
Patent number
7,733,888
Issue date
Jun 8, 2010
Alcatel-Lucent USA Inc.
Gregory S. Mathews
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information
Patent Grant
Flow control in a distributed scalable, shared memory switching fab...
Patent number
7,525,917
Issue date
Apr 28, 2009
Acatel-Lucent USA Inc.
Philip Ferolito
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information
Patent Grant
Using reassembly queue sets for packet reassembly
Patent number
7,394,822
Issue date
Jul 1, 2008
Lucent Technologies Inc.
Gregory S. Mathews
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information
Patent Grant
Random early drop with per hop behavior biasing
Patent number
7,349,336
Issue date
Mar 25, 2008
Lucent Technologies Inc.
Gregory Mathews
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information
Patent Grant
Circuit and method for protecting vector tags in high performance m...
Patent number
7,315,920
Issue date
Jan 1, 2008
Intel Corporation
Nhon Quach
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Optimal load balancing across multiple switching fabrics
Patent number
7,242,691
Issue date
Jul 10, 2007
Lucent Technologies Inc.
Gregory S. Mathews
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information
Patent Grant
Circuit and method for protecting 1-hot and 2-hot vector tags in hi...
Patent number
6,904,502
Issue date
Jun 7, 2005
Intel Corporation
Nhon Quach
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Circuit and method for protecting 1-hot and 2-hot vector tags in hi...
Patent number
6,839,814
Issue date
Jan 4, 2005
Intel Corporation
Nhon Quach
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Circuit and method for protecting 1-hot and 2-hot vector tags in hi...
Patent number
6,775,746
Issue date
Aug 10, 2004
Intel Corporation
Nhon Quach
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Efficient performance based scheduling mechanism for handling multi...
Patent number
6,728,800
Issue date
Apr 27, 2004
Intel Corporation
Allisa Chiao-Er Lee
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Processing ordered data requests to a memory
Patent number
6,725,339
Issue date
Apr 20, 2004
Intel Corporation
John Wai Cheong Fu
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Single bank associative cache
Patent number
6,687,790
Issue date
Feb 3, 2004
Intel Corporation
Edward Zager
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Method and apparatus to provide advanced load ordering
Patent number
6,681,317
Issue date
Jan 20, 2004
Intel Corporation
Gregory S. Mathews
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Apparatus and method for reducing power consumption due to cache an...
Patent number
6,678,815
Issue date
Jan 13, 2004
Intel Corporation
Gregory S. Mathews
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Circuit and method for protecting 1-hot and 2-hot vector tags in hi...
Patent number
6,675,266
Issue date
Jan 6, 2004
Intel Corporation
Nhon Quach
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Method and apparatus for advancing load operations
Patent number
6,658,559
Issue date
Dec 2, 2003
Intel Corporation
Judge Ken Arora
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
System and method for translation buffer accommodating multiple pag...
Patent number
6,625,715
Issue date
Sep 23, 2003
Intel Corporation
Gregory S. Mathews
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Method and apparatus for set associative cache tag error detection
Patent number
6,567,952
Issue date
May 20, 2003
Intel Corporation
Nhon Toai Quach
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
TLB using region ID prevalidation
Patent number
6,560,689
Issue date
May 6, 2003
Intel Corporation
Gregory S. Mathews
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Method and apparatus for managing temporal and non-temporal data in...
Patent number
6,542,966
Issue date
Apr 1, 2003
Intel Corporation
John Crawford
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
High performance fully dual-ported, pipelined cache design
Patent number
6,427,191
Issue date
Jul 30, 2002
Intel Corporation
John Wai Cheong Fu
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Hierarchical fully-associative-translation lookaside buffer structure
Patent number
6,418,521
Issue date
Jul 9, 2002
Intel Corporation
Gregory S. Mathews
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Unaligned semaphore adder
Patent number
6,405,233
Issue date
Jun 11, 2002
Intel Corporation
Gregory S. Mathews
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Processing ordered data requests to a memory
Patent number
6,381,678
Issue date
Apr 30, 2002
Intel Corporation
John Wai Cheong Fu
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Decentralized exception processing system
Patent number
6,282,636
Issue date
Aug 28, 2001
Intel Corporation
Tse-Yu Yeh
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Computer system having a set associative cache memory with sequenti...
Patent number
6,275,901
Issue date
Aug 14, 2001
Intel Corporation
Edward Zager
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Dual-ported, pipelined, two level cache system
Patent number
6,272,597
Issue date
Aug 7, 2001
Intel Corporation
John Wai Cheong Fu
G06 - COMPUTING CALCULATING COUNTING
Patents Applications
last 30 patents
Information
Patent Application
Communication Channels with both Shared and Independent Resources
Publication number
20230064187
Publication date
Mar 2, 2023
Apple Inc.
Rohit K. Gupta
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information
Patent Application
HIERARCHICAL RATE LIMITING WITH PROPORTIONAL LIMITING
Publication number
20080316921
Publication date
Dec 25, 2008
Gregory S. Mathews
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information
Patent Application
Circuit and method for protecting vector tags in high performance m...
Publication number
20050120184
Publication date
Jun 2, 2005
Intel Corporation
Nhon Quach
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
Circuit and method for protecting 1-hot and 2-hot vector tags in hi...
Publication number
20040139280
Publication date
Jul 15, 2004
Intel Corporation
Nhon T. Quach
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
Circuit and method for protecting 1-hot and 2-hot vector tags in hi...
Publication number
20040078529
Publication date
Apr 22, 2004
Intel Corporation
Nhon T. Quach
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
Testing and error recovery across multiple switching fabrics
Publication number
20040037277
Publication date
Feb 26, 2004
Gregory S. Mathews
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information
Patent Application
Pointer allocation by prime numbers
Publication number
20030235189
Publication date
Dec 25, 2003
Gregory S. Mathews
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information
Patent Application
Using reassembly queue sets for packet reassembly
Publication number
20030223458
Publication date
Dec 4, 2003
Gregory S. Mathews
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information
Patent Application
Flow control in a distributed scalable, shared memory switching fab...
Publication number
20030223448
Publication date
Dec 4, 2003
Philip Ferolito
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information
Patent Application
Random early drop with per hop behavior biasing
Publication number
20030223362
Publication date
Dec 4, 2003
Gregory Mathews
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information
Patent Application
Optimal load balancing across multiple switching fabrics
Publication number
20030223438
Publication date
Dec 4, 2003
Gregory S. Mathews
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information
Patent Application
Priority-biased exit queue arbitration with fairness
Publication number
20030225737
Publication date
Dec 4, 2003
Greg Mathews
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information
Patent Application
Circuit and method for protecting 1-hot and 2-hot vector tags in hi...
Publication number
20030196049
Publication date
Oct 16, 2003
Intel Corporation
Nhon Quach
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
System and method for translation buffer accommodating multiple pag...
Publication number
20030196066
Publication date
Oct 16, 2003
Intel Corporation
Gregory S. Mathews
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
Circuit and method for protecting 1-hot and 2-hot vector tags in hi...
Publication number
20020087808
Publication date
Jul 4, 2002
Nhon Quach
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
Processing ordered data requests to a memory
Publication number
20020073284
Publication date
Jun 13, 2002
John Wai Cheong Fu
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
Single bank associative cache
Publication number
20020029312
Publication date
Mar 7, 2002
Edward Zager
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
PROCESSING ORDERED DATA REQUESTS TO A MEMORY
Publication number
20010044881
Publication date
Nov 22, 2001
JOHN WAI CHEONG FU
G06 - COMPUTING CALCULATING COUNTING