Grigor S. Gasparyan

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Partition wire assignment for routing multi-partition circuit designs
- Patent number 11,238,206
- Issue date Feb 1, 2022
- Xilinx, Inc.
- Satish B. Sivaswamy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Serialization in electronic design automation flows
- Patent number 11,106,851
- Issue date Aug 31, 2021
- Xilinx, Inc.
- Paul D. Kundarewich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiprocessing flow and massively multi-threaded flow for multi-di...
- Patent number 11,003,827
- Issue date May 11, 2021
- Xilinx, Inc.
- Paul D. Kundarewich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data processing engine (DPE) array routing
- Patent number 10,963,615
- Issue date Mar 30, 2021
- Xilinx, Inc.
- Abhishek Joshi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Incremental initialization by parent and child placer processes in...
- Patent number 10,891,413
- Issue date Jan 12, 2021
- Xilinx, Inc.
- Paul D. Kundarewich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data processing engine (DPE) array global mapping
- Patent number 10,853,541
- Issue date Dec 1, 2020
- Xilinx, Inc.
- Abhishek Joshi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data processing engine (DPE) array detailed mapping
- Patent number 10,839,121
- Issue date Nov 17, 2020
- Xilinx, Inc.
- Abhishek Joshi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Netlist partitioning for designs targeting a data processing engine...
- Patent number 10,783,295
- Issue date Sep 22, 2020
- Xilinx, Inc.
- Xiao Dong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing closure of circuit designs for integrated circuits
- Patent number 10,366,201
- Issue date Jul 30, 2019
- Xilinx, Inc.
- Aaron Ng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing of a circuit design for debugging
- Patent number 10,126,361
- Issue date Nov 13, 2018
- Xilinx, Inc.
- Xiaojian Yang
- G01 - MEASURING TESTING
Information Patent Grant
Partitioning circuit designs for implementation within multi-die in...
- Patent number 10,108,773
- Issue date Oct 23, 2018
- Xilinx, Inc.
- Grigor S. Gasparyan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay modeling for high fan-out nets within circuit designs
- Patent number 10,108,769
- Issue date Oct 23, 2018
- Xilinx, Inc.
- Yau-Tsun S. Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multithreaded scheduling for placement of circuit designs using con...
- Patent number 9,529,957
- Issue date Dec 27, 2016
- Xilinx, Inc.
- Grigor S. Gasparyan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Re-budgeting connections of a circuit design
- Patent number 8,972,920
- Issue date Mar 3, 2015
- Xilinx, Inc.
- Grigor S. Gasparyan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Routing multi-fanout nets
- Patent number 8,959,474
- Issue date Feb 17, 2015
- Xilinx, Inc.
- Grigor S. Gasparyan
- G06 - COMPUTING CALCULATING COUNTING

Grigor S. Gasparyan

Person

Patents Grantslast 30 patents

Partition wire assignment for routing multi-partition circuit designs

Serialization in electronic design automation flows

Multiprocessing flow and massively multi-threaded flow for multi-di...

Data processing engine (DPE) array routing

Incremental initialization by parent and child placer processes in...

Data processing engine (DPE) array global mapping

Data processing engine (DPE) array detailed mapping

Netlist partitioning for designs targeting a data processing engine...

Timing closure of circuit designs for integrated circuits

Processing of a circuit design for debugging

Partitioning circuit designs for implementation within multi-die in...

Delay modeling for high fan-out nets within circuit designs

Multithreaded scheduling for placement of circuit designs using con...

Re-budgeting connections of a circuit design

Routing multi-fanout nets