Grzegorz Mrugalski

Person

Swardzez, PL

People

Patents Grantslast 30 patents

Information Patent Grant
Universal compactor architecture for testing circuits
- Patent number 11,815,555
- Issue date Nov 14, 2023
- SIEMENS INDUSTRY SOFTWARE INC.
- Yingdi Liu
- G01 - MEASURING TESTING
Information Patent Grant
Trajectory-optimized test pattern generation for built-in self-test
- Patent number 11,585,853
- Issue date Feb 21, 2023
- SIEMENS INDUSTRY SOFTWARE INC.
- Grzegorz Mrugalski
- G01 - MEASURING TESTING
Information Patent Grant
Suspect resolution for scan chain defect diagnosis
- Patent number 11,423,202
- Issue date Aug 23, 2022
- SIEMENS INDUSTRY SOFTWARE INC.
- Grzegorz Mrugalski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test scheduling and test access in test compression environment
- Patent number 10,955,460
- Issue date Mar 23, 2021
- Mentor Graphics Corporation
- Mark Kassab
- G01 - MEASURING TESTING
Information Patent Grant
Scan chain stitching for test-per-clock
- Patent number 10,379,161
- Issue date Aug 13, 2019
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Low power testing based on dynamic grouping of scan
- Patent number 10,120,029
- Issue date Nov 6, 2018
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Multi-stage test response compactors
- Patent number 10,120,024
- Issue date Nov 6, 2018
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Deterministic built-in self-test based on compressed test patterns...
- Patent number 9,933,485
- Issue date Apr 3, 2018
- Mentor Graphics Corporation
- Grzegorz Mrugalski
- G01 - MEASURING TESTING
Information Patent Grant
Selective per-cycle masking of scan chains for system level test
- Patent number 9,874,606
- Issue date Jan 23, 2018
- Mentor Graphics Corporation
- Janusz Rajski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-stage test response compactors
- Patent number 9,778,316
- Issue date Oct 3, 2017
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Test-per-clock based on dynamically-partitioned reconfigurable scan...
- Patent number 9,714,981
- Issue date Jul 25, 2017
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Selective per-cycle masking of scan chains for system level test
- Patent number 9,377,508
- Issue date Jun 28, 2016
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Test generation for test-per-clock
- Patent number 9,347,993
- Issue date May 24, 2016
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Test-per-clock based on dynamically-partitioned reconfigurable scan...
- Patent number 9,335,377
- Issue date May 10, 2016
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Test scheduling with pattern-independent test access mechanism
- Patent number 9,088,522
- Issue date Jul 21, 2015
- Mentor Graphics Corporation
- Janusz Rajski
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Scan chain configuration for test-per-clock based on circuit topology
- Patent number 9,009,553
- Issue date Apr 14, 2015
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Fault-driven scan chain configuration for test-per-clock
- Patent number 9,003,248
- Issue date Apr 7, 2015
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Low power compression of incompatible test cubes
- Patent number 8,832,512
- Issue date Sep 9, 2014
- Mentor Graphics Corporation
- Dariusz Czysz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selective per-cycle masking of scan chains for system level test
- Patent number 8,726,113
- Issue date May 13, 2014
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Test generator for low power built-in self-test
- Patent number 8,683,280
- Issue date Mar 25, 2014
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Compression based on deterministic vector clustering of incompatibl...
- Patent number 8,347,159
- Issue date Jan 1, 2013
- Mentor Graphics Corporation
- Grzegorz Mrugalski
- G01 - MEASURING TESTING
Information Patent Grant
Selective per-cycle masking of scan chains for system level test
- Patent number 8,166,359
- Issue date Apr 24, 2012
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
X-Masking for In-System Deterministic Test
- Publication number 20240337693
- Publication date Oct 10, 2024
- Siemens Industry Software Inc.
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
UNIVERSAL COMPACTOR ARCHITECTURE FOR TESTING CIRCUITS
- Publication number 20220308110
- Publication date Sep 29, 2022
- Siemens Industry Software Inc.
- Yingdi Liu
- G01 - MEASURING TESTING
Information Patent Application
SUSPECT RESOLUTION FOR SCAN CHAIN DEFECT DIAGNOSIS
- Publication number 20220065932
- Publication date Mar 3, 2022
- Mentor Graphics Corporation
- Grzegorz Mrugalski
- G01 - MEASURING TESTING
Information Patent Application
Trajectory-Optimized Test Pattern Generation for Built-In Self-Test
- Publication number 20210156918
- Publication date May 27, 2021
- Mentor Graphics Corporation
- Grzegorz Mrugalski
- G01 - MEASURING TESTING
Information Patent Application
MULTI-STAGE TEST RESPONSE COMPACTORS
- Publication number 20180156867
- Publication date Jun 7, 2018
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST
- Publication number 20180143249
- Publication date May 24, 2018
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST
- Publication number 20170052227
- Publication date Feb 23, 2017
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
MULTI-STAGE TEST RESPONSE COMPACTORS
- Publication number 20160320450
- Publication date Nov 3, 2016
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
TEST-PER-CLOCK BASED ON DYNAMICALLY-PARTITIONED RECONFIGURABLE SCAN...
- Publication number 20160252573
- Publication date Sep 1, 2016
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
Deterministic Built-In Self-Test
- Publication number 20160245863
- Publication date Aug 25, 2016
- Mentor Graphics Corporation
- Grzegorz Mrugalski
- G01 - MEASURING TESTING
Information Patent Application
Low Power Testing Based On Dynamic Grouping Of Scan
- Publication number 20150323597
- Publication date Nov 12, 2015
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
Test Scheduling and Test Access in Test Compression Environment
- Publication number 20150285854
- Publication date Oct 8, 2015
- Mark A. Kassab
- G01 - MEASURING TESTING
Information Patent Application
Fault-Driven Scan Chain Configuration For Test-Per-Clock
- Publication number 20140372820
- Publication date Dec 18, 2014
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
Scan Chain Stitching For Test-Per-Clock
- Publication number 20140372821
- Publication date Dec 18, 2014
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
Test Generation For Test-Per-Clock
- Publication number 20140372824
- Publication date Dec 18, 2014
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
Test-Per-Clock Based On Dynamically-Partitioned Reconfigurable Scan...
- Publication number 20140372818
- Publication date Dec 18, 2014
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
Scan Chain Configuration For Test-Per-Clock Based On Circuit Topology
- Publication number 20140372819
- Publication date Dec 18, 2014
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST
- Publication number 20140229779
- Publication date Aug 14, 2014
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
Test Scheduling With Pattern-Independent Test Access Mechanism
- Publication number 20130290795
- Publication date Oct 31, 2013
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST
- Publication number 20120210181
- Publication date Aug 16, 2012
- Mentor Graphics Corporation
- Janusz Rajski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Compression Based On Deterministic Vector Clustering Of Incompatibl...
- Publication number 20100229060
- Publication date Sep 9, 2010
- GRZEGORZ MRUGALSKI
- G01 - MEASURING TESTING
Information Patent Application
Selective Per-Cycle Masking Of Scan Chains For System Level Test
- Publication number 20090300446
- Publication date Dec 3, 2009
- Janusz Rajski
- G06 - COMPUTING CALCULATING COUNTING

Grzegorz Mrugalski

Person

Patents Grantslast 30 patents

Universal compactor architecture for testing circuits

Trajectory-optimized test pattern generation for built-in self-test

Suspect resolution for scan chain defect diagnosis

Test scheduling and test access in test compression environment

Scan chain stitching for test-per-clock

Low power testing based on dynamic grouping of scan

Multi-stage test response compactors

Deterministic built-in self-test based on compressed test patterns...

Selective per-cycle masking of scan chains for system level test

Multi-stage test response compactors

Test-per-clock based on dynamically-partitioned reconfigurable scan...

Selective per-cycle masking of scan chains for system level test

Test generation for test-per-clock

Test-per-clock based on dynamically-partitioned reconfigurable scan...

Test scheduling with pattern-independent test access mechanism

Scan chain configuration for test-per-clock based on circuit topology

Fault-driven scan chain configuration for test-per-clock

Low power compression of incompatible test cubes

Selective per-cycle masking of scan chains for system level test

Test generator for low power built-in self-test

Compression based on deterministic vector clustering of incompatibl...

Selective per-cycle masking of scan chains for system level test

Patents Applicationslast 30 patents

X-Masking for In-System Deterministic Test

UNIVERSAL COMPACTOR ARCHITECTURE FOR TESTING CIRCUITS

SUSPECT RESOLUTION FOR SCAN CHAIN DEFECT DIAGNOSIS

Trajectory-Optimized Test Pattern Generation for Built-In Self-Test

MULTI-STAGE TEST RESPONSE COMPACTORS

SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST

SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST

MULTI-STAGE TEST RESPONSE COMPACTORS

TEST-PER-CLOCK BASED ON DYNAMICALLY-PARTITIONED RECONFIGURABLE SCAN...

Deterministic Built-In Self-Test

Low Power Testing Based On Dynamic Grouping Of Scan

Test Scheduling and Test Access in Test Compression Environment

Fault-Driven Scan Chain Configuration For Test-Per-Clock

Scan Chain Stitching For Test-Per-Clock

Test Generation For Test-Per-Clock

Test-Per-Clock Based On Dynamically-Partitioned Reconfigurable Scan...

Scan Chain Configuration For Test-Per-Clock Based On Circuit Topology

SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST

Test Scheduling With Pattern-Independent Test Access Mechanism

SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST

Compression Based On Deterministic Vector Clustering Of Incompatibl...

Selective Per-Cycle Masking Of Scan Chains For System Level Test