Guenter Mayer

Person

Stuttgart, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Method and decimal arithmetic logic unit structure to generate a ma...
- Patent number 8,612,500
- Issue date Dec 17, 2013
- International Business Machines Corporation
- Wilhelm Haller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generating a local clock domain using dynamic controls
- Patent number 8,001,411
- Issue date Aug 16, 2011
- International Business Machines Corporation
- Sean Michael Carey
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit combining level shift function with gated reset
- Patent number 7,755,394
- Issue date Jul 13, 2010
- International Business Machines Corporation
- Thomas Froehnel
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Device for storing information and a method for partial write and r...
- Patent number 6,930,902
- Issue date Aug 16, 2005
- International Business Machines Corporation
- Guenter Mayer
- G11 - INFORMATION STORAGE
Information Patent Grant
Static logic compatible multiport latch
- Patent number 6,614,265
- Issue date Sep 2, 2003
- International Business Machines Corporation
- Stefan Buettner
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
SOI array sense and write margin qualification
- Patent number 6,341,093
- Issue date Jan 22, 2002
- International Business Machines Corporation
- Martin Eckert
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Verifying Simulation Design Modifications
- Publication number 20130096901
- Publication date Apr 18, 2013
- International Business Machines Corporation
- Wolfgang Gellerich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD TO PERFORM A SUBTRACTION OF TWO OPERANDS IN A BINARY ARITHME...
- Publication number 20090112963
- Publication date Apr 30, 2009
- International Business Machines Corporation
- Wilhelm Haller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Generating a Local Clock Domain Using Dynamic Controls
- Publication number 20090083569
- Publication date Mar 26, 2009
- International Business Machines Corporation
- Sean Michael Carey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Circuit Combining Level Shift Function with Gated Reset
- Publication number 20090058465
- Publication date Mar 5, 2009
- International Business Machines Corporation
- Thomas Froehnel
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method And Decimal Arithmetic Logic Unit Structure To Generate A Ma...
- Publication number 20080177816
- Publication date Jul 24, 2008
- International Business Machines Corporation
- Wilhelm Haller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD TO PERFORM A SUBTRACTION OF TWO OPERANDS IN A BINARY ARITHME...
- Publication number 20080071852
- Publication date Mar 20, 2008
- International Business Machines Corporation
- Wilhelm Haller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Device for storing information and a method for partial write and r...
- Publication number 20040109337
- Publication date Jun 10, 2004
- International Business Machines Corporation
- Guenter Mayer
- G11 - INFORMATION STORAGE
Information Patent Application
Static logic compatible multiport latch
- Publication number 20020149408
- Publication date Oct 17, 2002
- International Business Machines Corporation
- Stefan Buettner
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SOI array sense and write margin qualification
- Publication number 20020003733
- Publication date Jan 10, 2002
- International Business Machines Corporation
- Martin Eckert
- G11 - INFORMATION STORAGE

Guenter Mayer

Person

Patents Grantslast 30 patents

Method and decimal arithmetic logic unit structure to generate a ma...

Generating a local clock domain using dynamic controls

Circuit combining level shift function with gated reset

Device for storing information and a method for partial write and r...

Static logic compatible multiport latch

SOI array sense and write margin qualification

Patents Applicationslast 30 patents

Verifying Simulation Design Modifications

METHOD TO PERFORM A SUBTRACTION OF TWO OPERANDS IN A BINARY ARITHME...

Generating a Local Clock Domain Using Dynamic Controls

Circuit Combining Level Shift Function with Gated Reset

Method And Decimal Arithmetic Logic Unit Structure To Generate A Ma...

METHOD TO PERFORM A SUBTRACTION OF TWO OPERANDS IN A BINARY ARITHME...

Device for storing information and a method for partial write and r...

Static logic compatible multiport latch

SOI array sense and write margin qualification