Guenter Stenz

Person

Campbell, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Distributed parallel processing routing
- Patent number 11,875,100
- Issue date Jan 16, 2024
- Xilinx, Inc.
- Satish Sivaswamy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Serialization in electronic design automation flows
- Patent number 11,106,851
- Issue date Aug 31, 2021
- Xilinx, Inc.
- Paul D. Kundarewich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiprocessing flow and massively multi-threaded flow for multi-di...
- Patent number 11,003,827
- Issue date May 11, 2021
- Xilinx, Inc.
- Paul D. Kundarewich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Incremental initialization by parent and child placer processes in...
- Patent number 10,891,413
- Issue date Jan 12, 2021
- Xilinx, Inc.
- Paul D. Kundarewich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing optimizations in circuit designs using opposite clock edge t...
- Patent number 10,416,232
- Issue date Sep 17, 2019
- Xilinx, Inc.
- Guenter Stenz
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Vectorless dynamic power estimation for sequential circuits
- Patent number 9,881,112
- Issue date Jan 30, 2018
- Xilinx, Inc.
- Fan Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of placing input/output blocks on an integrated circuit device
- Patent number 8,312,405
- Issue date Nov 13, 2012
- Xilinx, Inc.
- Victor Slonim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placing complex function blocks on a programmable integrated circuit
- Patent number 8,082,532
- Issue date Dec 20, 2011
- Xilinx, Inc.
- Guenter Stenz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Assignment of select input/output blocks to banks for integrated ci...
- Patent number 8,010,924
- Issue date Aug 30, 2011
- Xilinx, Inc.
- Victor Z. Slonim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement of I/O blocks within I/O banks using an integer linear pr...
- Patent number 7,958,480
- Issue date Jun 7, 2011
- Xilinx, Inc.
- Victor Z. Slonim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods of structured placement of a circuit design
- Patent number 7,512,922
- Issue date Mar 31, 2009
- Xilinx, Inc.
- Guenter Stenz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement of input/output blocks of an electronic design in an inte...
- Patent number 7,392,499
- Issue date Jun 24, 2008
- Xilinx, Inc.
- Guenter Stenz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method system and apparatus for floorplanning programmable logic de...
- Patent number 7,313,778
- Issue date Dec 25, 2007
- Xilinx, Inc.
- Guenter Stenz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, system, and apparatus for incremental design in programmabl...
- Patent number 7,149,993
- Issue date Dec 12, 2006
- Xilinx, Inc.
- Rajat Aggarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for application of network flow techniques under constraints
- Patent number 7,143,380
- Issue date Nov 28, 2006
- Xilinx, Inc.
- Jason H. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Relocation of components for post-placement optimization
- Patent number 7,072,815
- Issue date Jul 4, 2006
- Xilinx, Inc.
- Kamal Chaudhary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Unified placer infrastructure
- Patent number 6,983,439
- Issue date Jan 3, 2006
- Xilinx, Inc.
- James L. Saunders
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Analytical placement methods with minimum preplaced components
- Patent number 6,957,406
- Issue date Oct 18, 2005
- Xilinx, Inc.
- Guenter Stenz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement of objects with partial shape restriction
- Patent number 6,857,115
- Issue date Feb 15, 2005
- Xilinx, Inc.
- Srinivasan Dasasathyan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement of clock objects under constraints
- Patent number 6,789,244
- Issue date Sep 7, 2004
- Xilinx, Inc.
- Srinivasan Dasasathyan
- G06 - COMPUTING CALCULATING COUNTING

Guenter Stenz

Person

Patents Grantslast 30 patents

Distributed parallel processing routing

Serialization in electronic design automation flows

Multiprocessing flow and massively multi-threaded flow for multi-di...

Incremental initialization by parent and child placer processes in...

Timing optimizations in circuit designs using opposite clock edge t...

Vectorless dynamic power estimation for sequential circuits

Method of placing input/output blocks on an integrated circuit device

Placing complex function blocks on a programmable integrated circuit

Assignment of select input/output blocks to banks for integrated ci...

Placement of I/O blocks within I/O banks using an integer linear pr...

Methods of structured placement of a circuit design

Placement of input/output blocks of an electronic design in an inte...

Method system and apparatus for floorplanning programmable logic de...

Method, system, and apparatus for incremental design in programmabl...

Method for application of network flow techniques under constraints

Relocation of components for post-placement optimization

Unified placer infrastructure

Analytical placement methods with minimum preplaced components

Placement of objects with partial shape restriction

Placement of clock objects under constraints