GuiChea Na

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Kyunggi-do, KR

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Patents Grantslast 30 patents

Information Patent Grant
Filp chip interconnection structure with bump on partial pad and me...
- Patent number 9,125,332
- Issue date Sep 1, 2015
- STATS ChipPAC, Ltd.
- Rajendra D. Pendse
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Integrated circuit package system with bump over via
- Patent number 8,592,989
- Issue date Nov 26, 2013
- Stats Chippac Ltd.
- Guichea Na
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Flip chip interconnection structure with bump on partial pad and me...
- Patent number 7,759,137
- Issue date Jul 20, 2010
- STATS ChipPAC, Ltd.
- Rajendra D. Pendse
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Patents Applicationslast 30 patents

Information Patent Application
Filp Chip Interconnection Structure with Bump on Partial Pad and Me...
- Publication number 20100244245
- Publication date Sep 30, 2010
- STATS ChipPAC, Ltd.
- Rajendra D. Pendse
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Flip Chip Interconnection Structure with Bump on Partial Pad and Me...
- Publication number 20090243080
- Publication date Oct 1, 2009
- STATS ChipPAC, Ltd.
- Rajendra D. Pendse
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH BUMP OVER VIA
- Publication number 20080191345
- Publication date Aug 14, 2008
- Guichea Na
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR