Guillaume Fortin

Person

Montreal, CA

People

Patents Grantslast 30 patents

Information Patent Grant
Data sampler with capacitive digital-to-analog converter
- Patent number 11,469,769
- Issue date Oct 11, 2022
- Cadence Design Systems, Inc.
- Louis-Francois Tanguay
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Continuous time linear equalization system and method
- Patent number 11,381,208
- Issue date Jul 5, 2022
- Cadence Design Systems, Inc.
- Clarence Kar Lun Tam
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Quarter-rate data sampling with loop-unrolled decision feedback equ...
- Patent number 11,356,304
- Issue date Jun 7, 2022
- Cadence Design Systems, Inc.
- Guillaume Fortin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Data sampling with loop-unrolled decision feedback equalization
- Patent number 11,323,117
- Issue date May 3, 2022
- Cadenee Design Systems, Inc.
- Louis-Francois Tanguay
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Duty cycle correction system and method
- Patent number 10,547,298
- Issue date Jan 28, 2020
- Cadence Design Systems, Inc.
- Rania Hassan Abdellatif Abdelrahim Mekky
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Adaptive pattern filtering for clock and data recovery to minimize...
- Patent number 10,355,889
- Issue date Jul 16, 2019
- Cadence Design Systems, Inc.
- Scott David Huss
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Low-frequency periodic signal detector
- Patent number 10,225,115
- Issue date Mar 5, 2019
- Cadence Design Systems, Inc.
- Mathieu Gagnon
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Boundary scan receiver
- Patent number 9,964,593
- Issue date May 8, 2018
- Cadence Design Systems, Inc.
- Guillaume Fortin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Tunable impedance circuit for a transmitter output stage
- Patent number 9,831,874
- Issue date Nov 28, 2017
- Cadence Design Systems, Inc.
- Guillaume Fortin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for interchangeable transmission driver output st...
- Patent number 9,705,499
- Issue date Jul 11, 2017
- Cadence Design Systems, Inc.
- Jean-Francois Delage
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for driving a laser diode
- Patent number 9,627,848
- Issue date Apr 18, 2017
- Microsemi Storage Solutions (U.S.), Inc.
- Jean-Francois Delage
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Active biasing in metal oxide semiconductor (MOS) differential pairs
- Patent number 9,325,305
- Issue date Apr 26, 2016
- Microsemi Storage Solutions, Inc.
- Guillaume Fortin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for driving a laser diode
- Patent number 9,252,563
- Issue date Feb 2, 2016
- PMC-Sierra US, Inc.
- Jean-François Delage
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Active biasing in metal oxide semiconductor (MOS) differential pairs
- Patent number 8,669,782
- Issue date Mar 11, 2014
- PMC-Sierra, Inc.
- Guillaume Fortin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock and data recovery locking technique for large frequency offsets
- Patent number 8,139,702
- Issue date Mar 20, 2012
- PMC-Sierra, Inc.
- Guillaume Fortin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Input/output interfacing with low power
- Patent number 8,018,251
- Issue date Sep 13, 2011
- PMC-Sierra, Inc.
- Graeme B. Boyd
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Active biasing in metal oxide semiconductor (MOS) differential pairs
- Patent number 7,969,195
- Issue date Jun 28, 2011
- PMC-Sierra, Inc.
- Guillaume Fortin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Variable-length digitally-controlled delay chain with interpolation...
- Patent number 7,884,660
- Issue date Feb 8, 2011
- PMC-Sierra, Inc.
- Jean-Francois Delage
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock and data recovery locking technique for large frequency offsets
- Patent number 7,738,617
- Issue date Jun 15, 2010
- PMC-Sierra, Inc.
- Guillaume Fortin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Variable-length digitally-controlled delay chain with interpolation...
- Patent number 7,733,149
- Issue date Jun 8, 2010
- PMC-Sierra, Inc.
- Jean-Francois Delage
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Active biasing in metal oxide semiconductor (MOS) differential pairs
- Patent number 7,471,107
- Issue date Dec 30, 2008
- PMC-Sierra, Inc.
- Guillaume Fortin
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Variable-Length Digitally-Controlled Delay Chain With Interpolation...
- Publication number 20100201418
- Publication date Aug 12, 2010
- PMC-Sierra, Inc.
- Jean-Francois Delage
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Variable-Length Digitally-Controlled Delay Chain with Interpolation...
- Publication number 20090309638
- Publication date Dec 17, 2009
- PMC-Sierra, Inc.
- Jean-Francois Delage
- H03 - BASIC ELECTRONIC CIRCUITRY

Guillaume Fortin

Person

Patents Grantslast 30 patents

Data sampler with capacitive digital-to-analog converter

Continuous time linear equalization system and method

Quarter-rate data sampling with loop-unrolled decision feedback equ...

Data sampling with loop-unrolled decision feedback equalization

Duty cycle correction system and method

Adaptive pattern filtering for clock and data recovery to minimize...

Low-frequency periodic signal detector

Boundary scan receiver

Tunable impedance circuit for a transmitter output stage

System and method for interchangeable transmission driver output st...

Method and apparatus for driving a laser diode

Active biasing in metal oxide semiconductor (MOS) differential pairs

Method and apparatus for driving a laser diode

Active biasing in metal oxide semiconductor (MOS) differential pairs

Clock and data recovery locking technique for large frequency offsets

Input/output interfacing with low power

Active biasing in metal oxide semiconductor (MOS) differential pairs

Variable-length digitally-controlled delay chain with interpolation...

Clock and data recovery locking technique for large frequency offsets

Variable-length digitally-controlled delay chain with interpolation...

Active biasing in metal oxide semiconductor (MOS) differential pairs

Patents Applicationslast 30 patents

Variable-Length Digitally-Controlled Delay Chain With Interpolation...

Variable-Length Digitally-Controlled Delay Chain with Interpolation...