Guillem Sole

Person

Barcelona, ES

People

Patents Grantslast 30 patents

Information Patent Grant
Bit shuffle processors, methods, systems, and instructions
- Patent number 10,713,044
- Issue date Jul 14, 2020
- Intel Corporation
- Roger Espasa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing a vector permute with an index...
- Patent number 10,445,092
- Issue date Oct 15, 2019
- Intel Corporation
- Jesus Corbal San Adrian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing a vector bit shuffle
- Patent number 10,296,489
- Issue date May 21, 2019
- Intel Corporation
- Elmoustapha Ould-Ahmed-Vall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing a vector bit gather
- Patent number 10,296,334
- Issue date May 21, 2019
- Intel Corporation
- Elmoustapha Ould-Ahmed-Vall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Three source operand floating-point addition instruction with opera...
- Patent number 9,785,433
- Issue date Oct 10, 2017
- Intel Corporation
- Roger Espasa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Consecutive bit error detection and correction
- Patent number 9,654,143
- Issue date May 16, 2017
- Intel Corporation
- Guillem Sole
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
BIT SHUFFLE PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
- Publication number 20210132950
- Publication date May 6, 2021
- Intel Corporation
- Roger Espasa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR PERFORMING A VECTOR PERMUTE WITH AN INDEX...
- Publication number 20200097290
- Publication date Mar 26, 2020
- Intel Corporation
- JESUS CORBAL SAN ADRIAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR VECTOR HORIZONTAL LOGICAL INSTRUCTION
- Publication number 20190138303
- Publication date May 9, 2019
- Intel Corporation
- Elmoustapha OULD-AHMED-VALL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THREE SOURCE OPERAND FLOATING-POINT ADDITION INSTRUCTION WITH OPERA...
- Publication number 20180032332
- Publication date Feb 1, 2018
- Intel Corporation
- Roger Espasa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BIT GROUP INTERLEAVE PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
- Publication number 20170308383
- Publication date Oct 26, 2017
- Intel Corporation
- Roger Espasa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BIT SHUFFLE PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
- Publication number 20170286112
- Publication date Oct 5, 2017
- Intel Corporation
- Roger Espasa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR VECTOR HORIZONTAL LOGICAL INSTRUCTION
- Publication number 20160283242
- Publication date Sep 29, 2016
- Intel Corporation
- Elmoustapha OULD-AHMED-VALL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR COMPRESSING A MASK VALUE
- Publication number 20160188333
- Publication date Jun 30, 2016
- Intel Coporation
- ELMOUSTAPHA OULD-AHMED-VALL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR PERFORMING A VECTOR BIT GATHER
- Publication number 20160188335
- Publication date Jun 30, 2016
- Intel Corporation
- ELMOUSTAPHA OULD-AHMED-VALL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR FUSED MULTIPLY-MULTIPLY INSTRUCTIONS
- Publication number 20160188327
- Publication date Jun 30, 2016
- Elmoustapha OULD-AHMED-VALL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR FUSED ADD-ADD INSTRUCTIONS
- Publication number 20160188341
- Publication date Jun 30, 2016
- Elmoustapha OULD-AHMED-VALL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR PERFORMING A VECTOR PERMUTE WITH AN INDEX...
- Publication number 20160188530
- Publication date Jun 30, 2016
- Intel Corporation
- JESUS CORBAL SAN ADRIAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR PERFORMING A VECTOR BIT SHUFFLE
- Publication number 20160188532
- Publication date Jun 30, 2016
- Intel Corporation
- ELMOUSTAPHA OULD-AHMED-VALL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR VECTOR BROADCAST AND XORAND LOGICAL INSTRU...
- Publication number 20160179523
- Publication date Jun 23, 2016
- Intel Corporation
- Elmoustapha OULD-AHMED-VALL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONSECUTIVE BIT ERROR DETECTION AND CORRECTION
- Publication number 20150370636
- Publication date Dec 24, 2015
- Guillem Sole
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THREE SOURCE OPERAND FLOATING POINT ADDITION PROCESSORS, METHODS, S...
- Publication number 20150286482
- Publication date Oct 8, 2015
- Intel Corporation
- Roger Espasa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR PERFORMING A PLURALITY OF MULTIPLICATION O...
- Publication number 20150277904
- Publication date Oct 1, 2015
- ROGER ESPASA
- G06 - COMPUTING CALCULATING COUNTING

Guillem Sole

Person

Patents Grantslast 30 patents

Bit shuffle processors, methods, systems, and instructions

Method and apparatus for performing a vector permute with an index...

Method and apparatus for performing a vector bit shuffle

Method and apparatus for performing a vector bit gather

Three source operand floating-point addition instruction with opera...

Consecutive bit error detection and correction

Patents Applicationslast 30 patents

BIT SHUFFLE PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS

METHOD AND APPARATUS FOR PERFORMING A VECTOR PERMUTE WITH AN INDEX...

APPARATUS AND METHOD FOR VECTOR HORIZONTAL LOGICAL INSTRUCTION

THREE SOURCE OPERAND FLOATING-POINT ADDITION INSTRUCTION WITH OPERA...

BIT GROUP INTERLEAVE PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS

BIT SHUFFLE PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS

APPARATUS AND METHOD FOR VECTOR HORIZONTAL LOGICAL INSTRUCTION

METHOD AND APPARATUS FOR COMPRESSING A MASK VALUE

METHOD AND APPARATUS FOR PERFORMING A VECTOR BIT GATHER

APPARATUS AND METHOD FOR FUSED MULTIPLY-MULTIPLY INSTRUCTIONS

APPARATUS AND METHOD FOR FUSED ADD-ADD INSTRUCTIONS

METHOD AND APPARATUS FOR PERFORMING A VECTOR PERMUTE WITH AN INDEX...

METHOD AND APPARATUS FOR PERFORMING A VECTOR BIT SHUFFLE

APPARATUS AND METHOD FOR VECTOR BROADCAST AND XORAND LOGICAL INSTRU...

CONSECUTIVE BIT ERROR DETECTION AND CORRECTION

THREE SOURCE OPERAND FLOATING POINT ADDITION PROCESSORS, METHODS, S...

METHOD AND APPARATUS FOR PERFORMING A PLURALITY OF MULTIPLICATION O...