Gunjan H. Pandya

Person

Beaverton, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Negative bitline write assist circuit and method for operating the...
- Patent number 10,902,893
- Issue date Jan 26, 2021
- Intel Corporation
- Pramod Kolar
- G11 - INFORMATION STORAGE
Information Patent Grant
Negative bitline write assist circuit and method for operating the...
- Patent number 10,818,326
- Issue date Oct 27, 2020
- Intel Corporation
- Pramod Kolar
- G11 - INFORMATION STORAGE
Information Patent Grant
Negative bitline write assist circuit and method for operating the...
- Patent number 9,818,460
- Issue date Nov 14, 2017
- Intel Corporation
- Pramod Kolar
- G11 - INFORMATION STORAGE
Information Patent Grant
Read and write apparatus and method for a dual port memory
- Patent number 9,812,189
- Issue date Nov 7, 2017
- Intel Corporation
- Pramod Kolar
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual-port static random access memory (SRAM)
- Patent number 9,607,687
- Issue date Mar 28, 2017
- Intel Corporation
- Pramod Kolar
- G11 - INFORMATION STORAGE
Information Patent Grant
Negative bitline write assist circuit and method for operating the...
- Patent number 9,378,788
- Issue date Jun 28, 2016
- Intel Corporation
- Pramod Kolar
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual-port static random access memory (SRAM)
- Patent number 9,208,853
- Issue date Dec 8, 2015
- Intel Corporation
- Pramod Kolar
- G11 - INFORMATION STORAGE
Information Patent Grant
Bitline floating during non-access mode for memory arrays
- Patent number 8,982,659
- Issue date Mar 17, 2015
- Intel Corporation
- Tsung-Yung Chang
- G11 - INFORMATION STORAGE
Information Patent Grant
Reducing minimum operating voltage through hybrid cache design
- Patent number 8,868,836
- Issue date Oct 21, 2014
- Intel Corporation
- Muhammad M. Khellah
- G11 - INFORMATION STORAGE
Information Patent Grant
Hierarchical DRAM sensing
- Patent number 8,406,073
- Issue date Mar 26, 2013
- Intel Corporation
- Dinesh Somasekhar
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory circuit
- Patent number 7,385,865
- Issue date Jun 10, 2008
- Intel Corporation
- Muhammad M. Khellah
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM with forward body biasing to improve read cell stability
- Patent number 6,985,380
- Issue date Jan 10, 2006
- Intel Corporation
- Muhammad M. Khellah
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
NEGATIVE BITLINE WRITE ASSIST CIRCUIT AND METHOD FOR OPERATING THE...
- Publication number 20180226109
- Publication date Aug 9, 2018
- Intel Corporation
- Pramod Kolar
- G11 - INFORMATION STORAGE
Information Patent Application
NEGATIVE BITLINE WRITE ASSIST CIRCUIT AND METHOD FOR OPERATING THE...
- Publication number 20180082722
- Publication date Mar 22, 2018
- Intel Corporation
- Pramod Kolar
- G11 - INFORMATION STORAGE
Information Patent Application
READ AND WRITE APPARATUS AND METHOD FOR A DUAL PORT MEMORY
- Publication number 20160358643
- Publication date Dec 8, 2016
- Intel Corporation
- Pramrod Kolar
- G11 - INFORMATION STORAGE
Information Patent Application
NEGATIVE BITLINE WRITE ASSIST CIRCUIT AND METHOD FOR OPERATING THE...
- Publication number 20160267952
- Publication date Sep 15, 2016
- Intel Corporation
- Pramod Kolar
- G11 - INFORMATION STORAGE
Information Patent Application
DUAL-PORT STATIC RANDOM ACCESS MEMORY (SRAM)
- Publication number 20160078926
- Publication date Mar 17, 2016
- Intel Corporation
- Pramod Kolar
- G11 - INFORMATION STORAGE
Information Patent Application
DUAL-PORT STATIC RANDOM ACCESS MEMORY (SRAM)
- Publication number 20140269019
- Publication date Sep 18, 2014
- Pramod Kolar
- G11 - INFORMATION STORAGE
Information Patent Application
NEGATIVE BITLINE WRITE ASSIST CIRCUIT AND METHOD FOR OPERATING THE...
- Publication number 20140169106
- Publication date Jun 19, 2014
- Pramod Kolar
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS ON DIRECT MATCHING OF CACHE TAGS CODED WITH ER...
- Publication number 20110161783
- Publication date Jun 30, 2011
- Dinesh Somasekhar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BITLINE FLOATING DURING NON-ACCESS MODE FOR MEMORY ARRAYS
- Publication number 20110149666
- Publication date Jun 23, 2011
- Tsung-Yung Chang
- G11 - INFORMATION STORAGE
Information Patent Application
Reducing minimum operating voltage through hybrid cache design
- Publication number 20090172283
- Publication date Jul 2, 2009
- Muhammad M. Khellah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory circuit
- Publication number 20060114711
- Publication date Jun 1, 2006
- Muhammad M. Khellah
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM WITH FORWARD BODY BIASING TO IMPROVE READ CELL STABILITY
- Publication number 20050213370
- Publication date Sep 29, 2005
- Muhammad M. Khellah
- G11 - INFORMATION STORAGE

Gunjan H. Pandya

Person

Patents Grantslast 30 patents

Negative bitline write assist circuit and method for operating the...

Negative bitline write assist circuit and method for operating the...

Negative bitline write assist circuit and method for operating the...

Read and write apparatus and method for a dual port memory

Dual-port static random access memory (SRAM)

Negative bitline write assist circuit and method for operating the...

Dual-port static random access memory (SRAM)

Bitline floating during non-access mode for memory arrays

Reducing minimum operating voltage through hybrid cache design

Hierarchical DRAM sensing

Memory circuit

SRAM with forward body biasing to improve read cell stability

Patents Applicationslast 30 patents

NEGATIVE BITLINE WRITE ASSIST CIRCUIT AND METHOD FOR OPERATING THE...

NEGATIVE BITLINE WRITE ASSIST CIRCUIT AND METHOD FOR OPERATING THE...

READ AND WRITE APPARATUS AND METHOD FOR A DUAL PORT MEMORY

NEGATIVE BITLINE WRITE ASSIST CIRCUIT AND METHOD FOR OPERATING THE...

DUAL-PORT STATIC RANDOM ACCESS MEMORY (SRAM)

DUAL-PORT STATIC RANDOM ACCESS MEMORY (SRAM)

NEGATIVE BITLINE WRITE ASSIST CIRCUIT AND METHOD FOR OPERATING THE...

METHOD AND APPARATUS ON DIRECT MATCHING OF CACHE TAGS CODED WITH ER...

BITLINE FLOATING DURING NON-ACCESS MODE FOR MEMORY ARRAYS

Reducing minimum operating voltage through hybrid cache design

Memory circuit

SRAM WITH FORWARD BODY BIASING TO IMPROVE READ CELL STABILITY