Gurbir Singh

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Enhanced highly pipelined bus architecture
- Patent number 6,907,487
- Issue date Jun 14, 2005
- Intel Corporation
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Snoop phase in a highly pipelined bus architecture
- Patent number 6,880,031
- Issue date Apr 12, 2005
- Intel Corporation
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Quad pumped bus architecture and protocol
- Patent number 6,807,592
- Issue date Oct 19, 2004
- Intel Corporation
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Response and data phases in a highly pipelined bus architecture
- Patent number 6,804,735
- Issue date Oct 12, 2004
- Intel Corporation
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing deferred transactions
- Patent number RE38388
- Issue date Jan 13, 2004
- Intel Corporation
- Nitin V. Sarangdhar
- 710 - Electrical computers and digital data processing systems: input/output
Information Patent Grant
Quad pumped bus architecture and protocol
- Patent number 6,609,171
- Issue date Aug 19, 2003
- Intel Corporation
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Quad pumped bus architecture and protocol
- Patent number 6,601,121
- Issue date Jul 29, 2003
- Intel Corporation
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data flow control mechanism for a bus supporting two-and three-agen...
- Patent number 6,405,271
- Issue date Jun 11, 2002
- Intel Corporation
- Peter D. MacWilliams
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for changing processor clock ratio settings
- Patent number 6,311,281
- Issue date Oct 30, 2001
- Edwin J. Pole
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor-cache protocol using simple commands to implement a range...
- Patent number 6,202,125
- Issue date Mar 13, 2001
- Intel Corporation
- Dan Patterson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Changing clock frequency
- Patent number 6,118,306
- Issue date Sep 12, 2000
- Intel Corporation
- John T. Orton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for caching lock conditions in a multi-process...
- Patent number 6,006,299
- Issue date Dec 21, 1999
- Intel Corporation
- Wen-Hann Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for controlling multiple dice with a single die
- Patent number 5,966,722
- Issue date Oct 12, 1999
- Intel Corporation
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing deferred transactions
- Patent number 5,937,171
- Issue date Aug 10, 1999
- Intel Corporation
- Nitin V. Sarangdhar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for ordering writeback data transfers on a bus
- Patent number 5,923,857
- Issue date Jul 13, 1999
- Intel Corporation
- Stephen S. Pawlowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for changing data transfer widths in a compute...
- Patent number 5,911,053
- Issue date Jun 8, 1999
- Intel Corporation
- Stephen S. Pawlowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing bus transactions in a computer...
- Patent number 5,903,738
- Issue date May 11, 1999
- Intel Corporation
- Nitin V. Sarangdhar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for maintaining cache coherency using a single...
- Patent number 5,903,908
- Issue date May 11, 1999
- Intel Corporation
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for maintaining cache coherency using a single...
- Patent number 5,832,534
- Issue date Nov 3, 1998
- Intel Corporation
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for cache memory replacement line identification
- Patent number 5,809,524
- Issue date Sep 15, 1998
- Intel Corporation
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Highly pipelined bus architecture
- Patent number 5,796,977
- Issue date Aug 18, 1998
- Intel Corporation
- Nitin V. Sarangdhar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for providing synchronous data transmission be...
- Patent number 5,754,833
- Issue date May 19, 1998
- Intel Corporation
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for maintaining multilevel cache hierarchy coherency in a...
- Patent number 5,715,428
- Issue date Feb 3, 1998
- Intel Corporation
- Wen-Hann Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for transferring information between a process...
- Patent number 5,701,503
- Issue date Dec 23, 1997
- Intel Corporation
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory subsystem wherein a single processor chip controls multiple...
- Patent number 5,678,020
- Issue date Oct 14, 1997
- Intel Corporation
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing deferred transactions
- Patent number 5,615,343
- Issue date Mar 25, 1997
- Intel Corporation
- Nitin V. Sarangdhar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer system with distributed bus arbitration scheme for symmetr...
- Patent number 5,581,782
- Issue date Dec 3, 1996
- Intel Corporation
- Nitin V. Sarangdhar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing bus transactions in a computer...
- Patent number 5,568,620
- Issue date Oct 22, 1996
- Intel Corporation
- Nitin V. Sarangdhar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microprocessor simultaneously issues an access to an external cache...
- Patent number 5,345,576
- Issue date Sep 6, 1994
- Intel Corporation
- Phillip G. Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable I/O sequencer for use in an I/O processor
- Patent number 4,803,622
- Issue date Feb 7, 1989
- Intel Corporation
- William L. Bain
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Response and data phases in a highly pipelined bus architecture
- Publication number 20020147875
- Publication date Oct 10, 2002
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Quad pumped bus architecture and protocol
- Publication number 20020038397
- Publication date Mar 28, 2002
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Quad pumped bus architecture and protocol
- Publication number 20020029307
- Publication date Mar 7, 2002
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Enhanced highly pipelined bus architecture
- Publication number 20010037421
- Publication date Nov 1, 2001
- Intel Corporation
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Snoop phase in a highly pipelined bus architecture
- Publication number 20010037424
- Publication date Nov 1, 2001
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING

Gurbir Singh

Person

Patents Grantslast 30 patents

Enhanced highly pipelined bus architecture

Snoop phase in a highly pipelined bus architecture

Quad pumped bus architecture and protocol

Response and data phases in a highly pipelined bus architecture

Method and apparatus for performing deferred transactions

Quad pumped bus architecture and protocol

Quad pumped bus architecture and protocol

Data flow control mechanism for a bus supporting two-and three-agen...

Apparatus and method for changing processor clock ratio settings

Processor-cache protocol using simple commands to implement a range...

Changing clock frequency

Apparatus and method for caching lock conditions in a multi-process...

Method and apparatus for controlling multiple dice with a single die

Method and apparatus for performing deferred transactions

Method and apparatus for ordering writeback data transfers on a bus

Method and apparatus for changing data transfer widths in a compute...

Method and apparatus for performing bus transactions in a computer...

Method and apparatus for maintaining cache coherency using a single...

Method and apparatus for maintaining cache coherency using a single...

Method and apparatus for cache memory replacement line identification

Highly pipelined bus architecture

Method and apparatus for providing synchronous data transmission be...

Apparatus for maintaining multilevel cache hierarchy coherency in a...

Method and apparatus for transferring information between a process...

Memory subsystem wherein a single processor chip controls multiple...

Method and apparatus for performing deferred transactions

Computer system with distributed bus arbitration scheme for symmetr...

Method and apparatus for performing bus transactions in a computer...

Microprocessor simultaneously issues an access to an external cache...

Programmable I/O sequencer for use in an I/O processor

Patents Applicationslast 30 patents

Response and data phases in a highly pipelined bus architecture

Quad pumped bus architecture and protocol

Quad pumped bus architecture and protocol

Enhanced highly pipelined bus architecture

Snoop phase in a highly pipelined bus architecture