Gururaj Shamanna

Person

Hillsboro, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Keeper-free integrated clock gate circuit
- Patent number 11,927,982
- Issue date Mar 12, 2024
- Intel Corporation
- Gururaj K. Shamanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low power clock gate circuit
- Patent number 10,996,709
- Issue date May 4, 2021
- Intel Corporation
- Gururaj Shamanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for adaptive write assist for memory
- Patent number 10,269,417
- Issue date Apr 23, 2019
- Intel Corporation
- Gururaj K. Shamanna
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for reducing leakage power of a circuit
- Patent number 9,921,630
- Issue date Mar 20, 2018
- Intel Corporation
- Gururaj K. Shamanna
- G05 - CONTROLLING REGULATING
Information Patent Grant
Apparatus and method for reducing leakage power of a circuit
- Patent number 9,207,750
- Issue date Dec 8, 2015
- Intel Corporation
- Gururaj K. Shamanna
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Avoiding tag compares during writes in multi-level cache hierarchy
- Patent number 6,321,297
- Issue date Nov 20, 2001
- Intel Corporation
- Gururaj Shamanna
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
VARIATION TOLERANT RECONFIGURABLE REPLICA BITLINE CIRCUITS
- Publication number 20230395140
- Publication date Dec 7, 2023
- Intel Corporation
- Naveen Kumar
- G11 - INFORMATION STORAGE
Information Patent Application
SELF-RESETTING CLOCK GENERATOR
- Publication number 20230343389
- Publication date Oct 26, 2023
- Intel Corporation
- Gururaj Shamanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD TO OPTIMIZE SENSE-AMP ENABLE PULSE-WIDTH IN SR...
- Publication number 20230123514
- Publication date Apr 20, 2023
- Intel Corporation
- Gururaj K. Shamanna
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAMMABLE CAPACITANCE IN THREE-DIMENSIONAL STACKED DIE ARCHITECTURE
- Publication number 20220375898
- Publication date Nov 24, 2022
- Intel Corporation
- Vishram Shriram Pandit
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
KEEPER-FREE INTEGRATED CLOCK GATE CIRCUIT
- Publication number 20220026945
- Publication date Jan 27, 2022
- Intel Corporation
- Gururaj K. Shamanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW POWER CLOCK GATE CIRCUIT
- Publication number 20210064076
- Publication date Mar 4, 2021
- Intel Corporation
- Gururaj Shamanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS FOR ADAPTIVE WRITE ASSIST FOR MEMORY
- Publication number 20170011793
- Publication date Jan 12, 2017
- Intell Corporation
- Gururaj K. SHAMANNA
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS AND METHOD FOR REDUCING LEAKAGE POWER OF A CIRCUIT
- Publication number 20160077567
- Publication date Mar 17, 2016
- Intel Corporation
- Gururaj K. Shamanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR REDUCING LEAKAGE POWER OF A CIRCUIT
- Publication number 20140173317
- Publication date Jun 19, 2014
- Gururaj K. Shamanna
- G06 - COMPUTING CALCULATING COUNTING

Gururaj Shamanna

Person

Patents Grantslast 30 patents

Keeper-free integrated clock gate circuit

Low power clock gate circuit

Apparatus for adaptive write assist for memory

Apparatus and method for reducing leakage power of a circuit

Apparatus and method for reducing leakage power of a circuit

Avoiding tag compares during writes in multi-level cache hierarchy

Patents Applicationslast 30 patents

VARIATION TOLERANT RECONFIGURABLE REPLICA BITLINE CIRCUITS

SELF-RESETTING CLOCK GENERATOR

APPARATUS AND METHOD TO OPTIMIZE SENSE-AMP ENABLE PULSE-WIDTH IN SR...

PROGRAMMABLE CAPACITANCE IN THREE-DIMENSIONAL STACKED DIE ARCHITECTURE

KEEPER-FREE INTEGRATED CLOCK GATE CIRCUIT

LOW POWER CLOCK GATE CIRCUIT

APPARATUS FOR ADAPTIVE WRITE ASSIST FOR MEMORY

APPARATUS AND METHOD FOR REDUCING LEAKAGE POWER OF A CIRCUIT

APPARATUS AND METHOD FOR REDUCING LEAKAGE POWER OF A CIRCUIT