Gurushankar Rajamani

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Systems for high-speed computing using an optical interchange
- Patent number 12,353,340
- Issue date Jul 8, 2025
- Google LLC
- Horia Alexandru Toma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory sparing to improve chip reliability
- Patent number 12,242,338
- Issue date Mar 4, 2025
- Google LLC
- Gurushankar Rajamani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Off-chip memory backed reliable transport connection cache hardware...
- Patent number 12,132,802
- Issue date Oct 29, 2024
- Google LLC
- Weihuang Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Vector reductions using shared scratchpad memory
- Patent number 11,934,826
- Issue date Mar 19, 2024
- Google LLC
- Thomas Norrie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interleaving memory requests to accelerate memory accesses
- Patent number 11,928,580
- Issue date Mar 12, 2024
- Google LLC
- Gurushankar Rajamani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data processing on memory controller
- Patent number 11,748,028
- Issue date Sep 5, 2023
- Google LLC
- Amin Farmahini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data processing on memory controller
- Patent number 11,513,724
- Issue date Nov 29, 2022
- Google LLC
- Amin Farmahini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interleaving memory requests to accelerate memory accesses
- Patent number 11,295,206
- Issue date Apr 5, 2022
- Google LLC
- Gurushankar Rajamani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Vector reductions using shared scratchpad memory
- Patent number 11,182,159
- Issue date Nov 23, 2021
- Google LLC
- Thomas Norrie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data processing on memory controller
- Patent number 11,137,936
- Issue date Oct 5, 2021
- Google LLC
- Amin Farmahini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bridging strongly ordered write transactions to devices in weakly o...
- Patent number 9,594,713
- Issue date Mar 14, 2017
- QUALCOMM Incorporated
- Randall John Pascarella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Self correction logic for serial-to-parallel converters
- Patent number 9,164,943
- Issue date Oct 20, 2015
- Intel Corporation
- Anil Sharma
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Increasing Input Output Hubs in constrained link based multi-proces...
- Patent number 8,782,318
- Issue date Jul 15, 2014
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Strategy to verify asynchronous links across chips
- Patent number 8,209,563
- Issue date Jun 26, 2012
- Intel Corporation
- Debendra Das Sharma
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Strategy to verify asynchronous links across chips
- Patent number 7,770,051
- Issue date Aug 3, 2010
- Intel Corporation
- Debendra Das Sharma
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Strategy to verify asynchronous links across chips
- Patent number 7,464,287
- Issue date Dec 9, 2008
- Intel Corporation
- Debendra Das Sharma
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multimodal optimization technique in test generation
- Patent number 6,810,372
- Issue date Oct 26, 2004
- Hewlett-Packard Development Company, L.P.
- Manoj Unnikrishnan
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
Memory Sparing to Improve Chip Reliability
- Publication number 20250103426
- Publication date Mar 27, 2025
- Google LLC
- Gurushankar Rajamani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems and Methods For High Bandwidth Memory With Unidirectional D...
- Publication number 20250045238
- Publication date Feb 6, 2025
- Google LLC
- Horia Alexandru Toma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems For High-Speed Computing Using An Optical Interchange
- Publication number 20250028661
- Publication date Jan 23, 2025
- Google LLC
- Horia Alexandru Toma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Sparing to Improve Chip Reliability
- Publication number 20240394141
- Publication date Nov 28, 2024
- Google LLC
- Gurushankar Rajamani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA PROCESSING ON MEMORY CONTROLLER
- Publication number 20230161498
- Publication date May 25, 2023
- Google LLC
- Amin Farmahini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Off-Chip Memory Backed Reliable Transport Connection Cache Hardware...
- Publication number 20230062889
- Publication date Mar 2, 2023
- Google LLC
- Weihuang Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERLEAVING MEMORY REQUESTS TO ACCELERATE MEMORY ACCESSES
- Publication number 20220374692
- Publication date Nov 24, 2022
- Google LLC
- Gurushankar Rajamani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VECTOR REDUCTIONS USING SHARED SCRATCHPAD MEMORY
- Publication number 20220156071
- Publication date May 19, 2022
- Google LLC
- Thomas Norrie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA PROCESSING ON MEMORY CONTROLLER
- Publication number 20210311658
- Publication date Oct 7, 2021
- Google LLC
- Amin Farmahini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VECTOR REDUCTIONS USING SHARED SCRATCHPAD MEMORY
- Publication number 20210263739
- Publication date Aug 26, 2021
- Google LLC
- Thomas Norrie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERLEAVING MEMORY REQUESTS TO ACCELERATE MEMORY ACCESSES
- Publication number 20210248451
- Publication date Aug 12, 2021
- Google LLC
- Gurushankar Rajamani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA PROCESSING ON MEMORY CONTROLLER
- Publication number 20210223985
- Publication date Jul 22, 2021
- Google LLC
- Amin Farmahini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BRIDGING STRONGLY ORDERED WRITE TRANSACTIONS TO DEVICES IN WEAKLY O...
- Publication number 20160077991
- Publication date Mar 17, 2016
- QUALCOMM Incorporated
- Randall John Pascarella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELF CORRECTION LOGIC FOR SERIAL-TO-PARALLEL CONVERTERS
- Publication number 20140223045
- Publication date Aug 7, 2014
- Anil Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INCREASING INPUT OUTPUT HUBS IN CONSTRAINED LINK BASED MULTI-PROCES...
- Publication number 20120226848
- Publication date Sep 6, 2012
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STRATEGY TO VERIFY ASYNCHRONOUS LINKS ACROSS CHIPS
- Publication number 20100199120
- Publication date Aug 5, 2010
- Debendra Das Sharma
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Strategy to Verify Asynchronous Links Across Chips
- Publication number 20090016381
- Publication date Jan 15, 2009
- Debendra Das Sharma
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Strategy to verify asynchronous links across chips
- Publication number 20050220121
- Publication date Oct 6, 2005
- Debendra Das Sharma
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and apparatus for stressing data paths
- Publication number 20040078712
- Publication date Apr 22, 2004
- Gurushankar Rajamani
- G06 - COMPUTING CALCULATING COUNTING

Gurushankar Rajamani

Person

Patents Grantslast 30 patents

Systems for high-speed computing using an optical interchange

Memory sparing to improve chip reliability

Off-chip memory backed reliable transport connection cache hardware...

Vector reductions using shared scratchpad memory

Interleaving memory requests to accelerate memory accesses

Data processing on memory controller

Data processing on memory controller

Interleaving memory requests to accelerate memory accesses

Vector reductions using shared scratchpad memory

Data processing on memory controller

Bridging strongly ordered write transactions to devices in weakly o...

Self correction logic for serial-to-parallel converters

Increasing Input Output Hubs in constrained link based multi-proces...

Strategy to verify asynchronous links across chips

Strategy to verify asynchronous links across chips

Strategy to verify asynchronous links across chips

Multimodal optimization technique in test generation

Patents Applicationslast 30 patents

Memory Sparing to Improve Chip Reliability

Systems and Methods For High Bandwidth Memory With Unidirectional D...

Systems For High-Speed Computing Using An Optical Interchange

Memory Sparing to Improve Chip Reliability

DATA PROCESSING ON MEMORY CONTROLLER

Off-Chip Memory Backed Reliable Transport Connection Cache Hardware...

INTERLEAVING MEMORY REQUESTS TO ACCELERATE MEMORY ACCESSES

VECTOR REDUCTIONS USING SHARED SCRATCHPAD MEMORY

DATA PROCESSING ON MEMORY CONTROLLER

VECTOR REDUCTIONS USING SHARED SCRATCHPAD MEMORY

INTERLEAVING MEMORY REQUESTS TO ACCELERATE MEMORY ACCESSES

DATA PROCESSING ON MEMORY CONTROLLER

BRIDGING STRONGLY ORDERED WRITE TRANSACTIONS TO DEVICES IN WEAKLY O...

SELF CORRECTION LOGIC FOR SERIAL-TO-PARALLEL CONVERTERS

INCREASING INPUT OUTPUT HUBS IN CONSTRAINED LINK BASED MULTI-PROCES...

STRATEGY TO VERIFY ASYNCHRONOUS LINKS ACROSS CHIPS

Strategy to Verify Asynchronous Links Across Chips

Strategy to verify asynchronous links across chips

Method and apparatus for stressing data paths