Guy Dupenloup

Person

Marly-le-Roi, FR

People

Patents Grantslast 30 patents

Information Patent Grant
Automatic synthesis script generation for synopsys design compiler
- Patent number 6,836,877
- Issue date Dec 28, 2004
- LSI Logic Corporation
- Guy Dupenloup
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient top-down characterization method
- Patent number 6,421,818
- Issue date Jul 16, 2002
- LSI Logic Corporation
- Guy Dupenloup
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of handling macro components in circuit design synthesis
- Patent number 6,378,123
- Issue date Apr 23, 2002
- LSI Logic Corporation
- Guy Dupenloup
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
RTL analysis for improved logic synthesis
- Patent number 6,295,636
- Issue date Sep 25, 2001
- LSI Logic Corporation
- Guy Dupenloup
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
RTL analysis tool
- Patent number 6,292,931
- Issue date Sep 18, 2001
- LSI Logic Corporation
- Guy Dupenloup
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Netlist analysis tool by degree of conformity
- Patent number 6,289,491
- Issue date Sep 11, 2001
- LSI Logic Corporation
- Guy Dupenloup
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
VDHL/Verilog expertise and gate synthesis automation system
- Patent number 6,289,498
- Issue date Sep 11, 2001
- LSI Logic Corporation
- Guy Dupenloup
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of accessing the generic netlist created by synopsys design...
- Patent number 6,263,483
- Issue date Jul 17, 2001
- LSI Logic Corporation
- Guy Dupenloup
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Buffering tree analysis in mapped design
- Patent number 6,205,572
- Issue date Mar 20, 2001
- LSI Logic Corporation
- Guy Dupenloup
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Internal clock handling in synthesis script
- Patent number 6,173,435
- Issue date Jan 9, 2001
- LSI Logic Corporation
- Guy Dupenloup
- G06 - COMPUTING CALCULATING COUNTING

Guy Dupenloup

Person

Patents Grantslast 30 patents

Automatic synthesis script generation for synopsys design compiler

Efficient top-down characterization method

Method of handling macro components in circuit design synthesis

RTL analysis for improved logic synthesis

RTL analysis tool

Netlist analysis tool by degree of conformity

VDHL/Verilog expertise and gate synthesis automation system

Method of accessing the generic netlist created by synopsys design...

Buffering tree analysis in mapped design

Internal clock handling in synthesis script