Guy F. Burgess

Person

Gilbert, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Methods for forming pillar bumps on semiconductor wafers
- Patent number 9,831,201
- Issue date Nov 28, 2017
- Guy F. Burgess
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for building vertical pillar interconnect
- Patent number 9,627,254
- Issue date Apr 18, 2017
- Guy F. Burgess
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electroplating using dielectric bridges
- Patent number 9,070,747
- Issue date Jun 30, 2015
- FlipChip International LLC
- Eugene A. Stout
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for applying a final metal layer for wafer level packaging a...
- Patent number 8,980,743
- Issue date Mar 17, 2015
- FlipChip International LLC
- Guy F. Burgess
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer-level interconnect for high mechanical reliability applications
- Patent number 8,754,524
- Issue date Jun 17, 2014
- FlipChip International, LLC
- Anthony Curtis
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Wafer-level interconnect for high mechanical reliability applications
- Patent number 8,143,722
- Issue date Mar 27, 2012
- FlipChip International, LLC
- Anthony Curtis
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Enhanced reliability for semiconductor devices using dielectric enc...
- Patent number 8,058,163
- Issue date Nov 15, 2011
- FlipChip International, LLC
- John J. H. Reche
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHODS FOR FORMING PILLAR BUMPS ON SEMICONDUCTOR WAFERS
- Publication number 20160268223
- Publication date Sep 15, 2016
- Flipchip International LLC
- Guy F. Burgess
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR APPLYING A FINAL METAL LAYER FOR WAFER LEVEL PACKAGING A...
- Publication number 20150270223
- Publication date Sep 24, 2015
- Guy F. Burgess
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTROPLATING USING DIELECTRIC BRIDGES
- Publication number 20150001684
- Publication date Jan 1, 2015
- FlipChip International, LLC
- Eugene A. Stout
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR APPLYING A FINAL METAL LAYER FOR WAFER LEVEL PACKAGING A...
- Publication number 20130328203
- Publication date Dec 12, 2013
- FlipChip International, LLC
- Guy F. Burgess
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR BUILDING VERTICAL PILLAR INTERCONNECT
- Publication number 20130196499
- Publication date Aug 1, 2013
- FlipChip International, LLC
- Guy F. Burgess
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER-LEVEL INTERCONNECT FOR HIGH MECHANICAL RELIABILITY APPLICATIONS
- Publication number 20120146219
- Publication date Jun 14, 2012
- FlipChip International, LLC
- Anthony Curtis
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
METHODS AND STRUCTURES FOR A VERTICAL PILLAR INTERCONNECT
- Publication number 20110003470
- Publication date Jan 6, 2011
- FlipChip International, LLC
- Guy F. Burgess
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ENHANCED RELIABILITY FOR SEMICONDUCTOR DEVICES USING DIELECTRIC ENC...
- Publication number 20100032836
- Publication date Feb 11, 2010
- FlipChip International, LLC
- John J.H. Reche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER-LEVEL INTERCONNECT FOR HIGH MECHANICAL RELIABILITY APPLICATIONS
- Publication number 20080083986
- Publication date Apr 10, 2008
- Anthony Curtis
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR

Guy F. Burgess

Person

Patents Grantslast 30 patents

Methods for forming pillar bumps on semiconductor wafers

Method for building vertical pillar interconnect

Electroplating using dielectric bridges

Method for applying a final metal layer for wafer level packaging a...

Wafer-level interconnect for high mechanical reliability applications

Wafer-level interconnect for high mechanical reliability applications

Enhanced reliability for semiconductor devices using dielectric enc...

Patents Applicationslast 30 patents

METHODS FOR FORMING PILLAR BUMPS ON SEMICONDUCTOR WAFERS

METHOD FOR APPLYING A FINAL METAL LAYER FOR WAFER LEVEL PACKAGING A...

ELECTROPLATING USING DIELECTRIC BRIDGES

METHOD FOR APPLYING A FINAL METAL LAYER FOR WAFER LEVEL PACKAGING A...

METHOD FOR BUILDING VERTICAL PILLAR INTERCONNECT

WAFER-LEVEL INTERCONNECT FOR HIGH MECHANICAL RELIABILITY APPLICATIONS

METHODS AND STRUCTURES FOR A VERTICAL PILLAR INTERCONNECT

ENHANCED RELIABILITY FOR SEMICONDUCTOR DEVICES USING DIELECTRIC ENC...

WAFER-LEVEL INTERCONNECT FOR HIGH MECHANICAL RELIABILITY APPLICATIONS