Haisong WANG

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Crissier, CH

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Patents Grantslast 30 patents

Information Patent Grant
Multiplying delay-locked loop using sampling time-to-digital converter
- Patent number 10,250,264
- Issue date Apr 2, 2019
- Marvell World Trade Ltd.
- Haisong Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
All-digital phase locked loop (ADPLL) including a digital-to-time c...
- Patent number 9,740,175
- Issue date Aug 22, 2017
- Marvell World Trade Ltd.
- Olivier Burg
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
MULTIPLYING DELAY-LOCKED LOOP USING SAMPLING TIME-TO-DIGITAL CONVERTER
- Publication number 20170366191
- Publication date Dec 21, 2017
- Marvell World Trade Ltd.
- Haisong Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ANALOG FRACTIONAL-N PHASE-LOCKED LOOP
- Publication number 20170366376
- Publication date Dec 21, 2017
- Marvell World Trade Ltd.
- Haisong Wang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
ALL-DIGITAL PHASE LOCKED LOOP (ADPLL) INCLUDING A DIGITAL-TO-TIME C...
- Publication number 20170205772
- Publication date Jul 20, 2017
- Marvell World Trade Ltd.
- Olivier BURG
- G04 - HOROLOGY