Haizhou Chen

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Santa Clara, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Timing, noise, and power analysis of integrated circuits
- Patent number 8,225,248
- Issue date Jul 17, 2012
- Cadence Design Systems, Inc.
- Haizhou Chen
- G05 - CONTROLLING REGULATING
Information Patent Grant
Modeling device variations in integrated circuit design
- Patent number 7,673,260
- Issue date Mar 2, 2010
- Cadence Design Systems, Inc.
- Haizhou Chen
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Modeling device variations in integrated circuit design
- Publication number 20070099314
- Publication date May 3, 2007
- Haizhou Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Timing, noise, and power analysis of integrated circuits
- Publication number 20070094623
- Publication date Apr 26, 2007
- Haizhou Chen
- G06 - COMPUTING CALCULATING COUNTING