Hang-Shing MA

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Portland, OR, US

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Patents Grantslast 30 patents

Information Patent Grant
3D interconnect structure comprising through-silicon vias combined...
- Patent number 9,530,740
- Issue date Dec 27, 2016
- Intel Corporation
- Kevin J. Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D interconnect structure comprising fine pitch single damascene ba...
- Patent number 9,449,913
- Issue date Sep 20, 2016
- Intel Corporation
- Kevin J. Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D interconnect structure comprising through-silicon vias combined...
- Patent number 9,142,510
- Issue date Sep 22, 2015
- Intel Corporation
- Kevin J. Lee
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
3D INTERCONNECT STRUCTURE COMPRISING THROUGH-SILICON VIAS COMBINED...
- Publication number 20150364425
- Publication date Dec 17, 2015
- Intel Corporation
- Kevin J. Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D INTERCONNECT STRUCTURE COMPRISING THROUGH-SILICON VIAS COMBINED...
- Publication number 20130285257
- Publication date Oct 31, 2013
- Kevin J. Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D INTERCONNECT STRUCTURE COMPRISING FINE PITCH SINGLE DAMASCENE BA...
- Publication number 20130256910
- Publication date Oct 3, 2013
- Kevin J. Lee
- H01 - BASIC ELECTRIC ELEMENTS