Hans Erich Multhaup

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Odelzhausen, DE

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Patents Grantslast 30 patents

Information Patent Grant
Full memory logical erase for circuit verification
- Patent number 10,546,081
- Issue date Jan 28, 2020
- Mentor Graphics Corporation
- Khaled Salah Mohamed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method of clocking an IP core during a debugging operation
- Patent number 8,086,921
- Issue date Dec 27, 2011
- Mentor Graphics Corporation
- Greg Bensinger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method of clocking an IP core during a debugging operation
- Patent number 7,676,712
- Issue date Mar 9, 2010
- Mentor Graphics Corporation
- Greg Bensinger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Accelerated hardware emulation environment for processor-based systems
- Patent number 7,475,288
- Issue date Jan 6, 2009
- Hans Erich Multhaup
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Full Memory Logical Erase For Circuit Verification
- Publication number 20190087522
- Publication date Mar 21, 2019
- Mentor Graphics Corporation
- Khaled Salah Mohamed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Method of Clocking an IP Core During a Debugging Operation
- Publication number 20100313058
- Publication date Dec 9, 2010
- Mentor Graphics Corporation
- Greg Bensinger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Accelerated hardware emulation environment for processor-based systems
- Publication number 20060143522
- Publication date Jun 29, 2006
- Hans Erich Multhaup
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method of clocking an ip core during a debugging operation
- Publication number 20060059388
- Publication date Mar 16, 2006
- Greg Bensinger
- G06 - COMPUTING CALCULATING COUNTING