Haoxing Ren

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Rail power density aware standard cell placement for integrated cir...
- Patent number 12,277,376
- Issue date Apr 15, 2025
- NVIDIA Corporation
- Shaurakar Das
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout parasitics and device parameter prediction using graph neura...
- Patent number 12,217,151
- Issue date Feb 4, 2025
- NVIDIA Corp.
- Haoxing Ren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Standard cell layout generation with applied artificial intelligence
- Patent number 12,169,677
- Issue date Dec 17, 2024
- NVIDIA Corp.
- Haoxing Ren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fine-grained per-vector scaling for neural network quantization
- Patent number 12,045,307
- Issue date Jul 23, 2024
- NVIDIA Corporation
- Brucek Kurdo Khailany
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Routing connections in integrated circuits based on reinforcement l...
- Patent number 12,019,967
- Issue date Jun 25, 2024
- NVIDIA Corporation
- Haoxing Ren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Rail power density aware standard cell placement for integrated cir...
- Patent number 11,972,188
- Issue date Apr 30, 2024
- NVIDIA Corporation
- Shaurakar Das
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout parasitics and device parameter prediction using graph neura...
- Patent number 11,651,194
- Issue date May 16, 2023
- NVIDIA Corp.
- Haoxing Ren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
IR drop prediction with maximum convolutional neural network
- Patent number 11,645,533
- Issue date May 9, 2023
- NVIDIA Corp.
- Zhiyao Xie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit design changes using through-silicon vias
- Patent number 10,956,644
- Issue date Mar 23, 2021
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Deep learning testability analysis with graph convolutional networks
- Patent number 10,657,306
- Issue date May 19, 2020
- NVIDIA Corp.
- Yuzhe Ma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
LLVM-based system C compiler for architecture synthesis
- Patent number 10,545,739
- Issue date Jan 28, 2020
- International Business Machines Corporation
- Minsik Cho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synthesis for random testability using unreachable states in integr...
- Patent number 10,502,782
- Issue date Dec 10, 2019
- International Business Machines Corporation
- Victor N. Kravets
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit design changes using through-silicon vias
- Patent number 10,223,491
- Issue date Mar 5, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automating a microarchitecture design exploration environment
- Patent number 9,665,674
- Issue date May 30, 2017
- International Business Machines Corporation
- Minsik Cho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Through-silicon via access device for integrated circuits
- Patent number 9,633,928
- Issue date Apr 25, 2017
- International Business Machines Corporation
- Harry Barowski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit design changes using through-silicon vias
- Patent number 9,569,580
- Issue date Feb 14, 2017
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement aware functional engineering change order extraction
- Patent number 9,563,736
- Issue date Feb 7, 2017
- International Business Machines Corporation
- George Antony
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automating a microarchitecture design exploration environment
- Patent number 9,507,891
- Issue date Nov 29, 2016
- International Business Machines Corporation
- Minsik Cho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit design changes using through-silicon vias
- Patent number 9,501,603
- Issue date Nov 22, 2016
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automating a microarchitecture design exploration environment
- Patent number 9,477,797
- Issue date Oct 25, 2016
- International Business Machines Corporation
- Minsik Cho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Through-silicon via access device for integrated circuits
- Patent number 9,412,682
- Issue date Aug 9, 2016
- International Business Machines Corporation
- Harry Barowski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Automating a microarchitecture design exploration environment
- Patent number 9,405,866
- Issue date Aug 2, 2016
- International Business Machines Corporation
- Minsik Cho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Relative ordering circuit synthesis
- Patent number 8,756,541
- Issue date Jun 17, 2014
- International Business Machines Corporation
- Minsik Cho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automated critical area allocation in a physical synthesized hierar...
- Patent number 8,656,332
- Issue date Feb 18, 2014
- International Business Machines Corporation
- Bruce M. Fleischer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Network flow based datapath bit slicing
- Patent number 8,566,761
- Issue date Oct 22, 2013
- International Business Machines Corporation
- Hua Xiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Soft hierarchy-based physical synthesis for large-scale, high-perfo...
- Patent number 8,516,412
- Issue date Aug 20, 2013
- International Business Machines Corporation
- Minsik Cho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structured latch and local-clock-buffer planning
- Patent number 8,495,552
- Issue date Jul 23, 2013
- International Business Machines Corporation
- Minsik Cho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic modification synthesis for high performance circuits
- Patent number 8,468,477
- Issue date Jun 18, 2013
- International Business Machines Corporation
- Haoxing Ren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic modification synthesis
- Patent number 8,365,114
- Issue date Jan 29, 2013
- International Business Machines Corporation
- Eli Arbel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Converged large block and structured synthesis for high performance...
- Patent number 8,271,920
- Issue date Sep 18, 2012
- International Business Machines Corporation
- Minsik Cho
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
AERIAL IMAGE GENERATION THROUGH PHYSICS-INFORMED KERNEL LEARNING
- Publication number 20250238893
- Publication date Jul 24, 2025
- NVIDIA Corp.
- Haoyu Yang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LEARNING-BASED PLACEMENT FOR CONGESTION MITIGATION
- Publication number 20250181806
- Publication date Jun 5, 2025
- NVIDIA Corp.
- Anthony Dimitri Armand Agnesina
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIFFERENTIABLE GLOBAL ROUTER
- Publication number 20250181814
- Publication date Jun 5, 2025
- NVIDIA Corp.
- Rongjian Liang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSFORMER MODEL-BASED CLUSTERING TECHNIQUES FOR STANDARD CELL DES...
- Publication number 20250111112
- Publication date Apr 3, 2025
- NVIDIA Corporation
- Chia-Tung HO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PIN DENSITY-BASED CONGESTION ESTIMATION FOR ROUTABILITY-DRIVEN STAN...
- Publication number 20240411974
- Publication date Dec 12, 2024
- NVIDIA Corp.
- Chia-Tung HO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC STANDARD CELL EXTERNAL PIN METHODOLOGY FOR ROUTABILITY-DRIV...
- Publication number 20240411977
- Publication date Dec 12, 2024
- NVIDIA Corp.
- Chia-Tung HO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RAIL POWER DENSITY AWARE STANDARD CELL PLACEMENT FOR INTEGRATED CIR...
- Publication number 20240256753
- Publication date Aug 1, 2024
- NVIDIA Corporation
- Shaurakar Das
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MACHINE LEARNING FOR MASK OPTIMIZATION IN INVERSE LITHOGRAPHY TECHN...
- Publication number 20240168390
- Publication date May 23, 2024
- NVIDIA Corporation
- Haoyu Yang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR GENERATING DESIGNS OF CIRCUITS THAT INCLUDE BUFFERS...
- Publication number 20240104283
- Publication date Mar 28, 2024
- NVIDIA Corporation
- Rongjian LIANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LARGE SCALE MASK OPTIMIZATION WITH CONVOLUTIONAL FOURIER NEURAL OPE...
- Publication number 20240013033
- Publication date Jan 11, 2024
- NVIDIA Corp.
- Haoyu Yang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VLSI PLACEMENT OPTIMIZATION USING SELF-SUPERVISED GRAPH CLUSTERING
- Publication number 20230376659
- Publication date Nov 23, 2023
- NVIDIA Corporation
- Yi-Chen Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GENERATIVE SELF-SUPERVISED LEARNING TO TRANSFORM CIRCUIT NETLISTS
- Publication number 20230334215
- Publication date Oct 19, 2023
- NVIDIA Corp.
- Siddhartha Nath
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Layout Parasitics and Device Parameter Prediction using Graph Neura...
- Publication number 20230237313
- Publication date Jul 27, 2023
- NVIDIA Corp.
- Haoxing Ren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LITHOGRAPHY SIMULATION USING A NEURAL NETWORK
- Publication number 20230153510
- Publication date May 18, 2023
- NVIDIA Corporation
- Haoyu Yang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RAIL POWER DENSITY AWARE STANDARD CELL PLACEMENT FOR INTEGRATED CIR...
- Publication number 20230130642
- Publication date Apr 27, 2023
- NVIDIA Corporation
- Shaurakar Das
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCING CROSSTALK PESSIMISM USING GPU-ACCELERATED GATE SIMULATION...
- Publication number 20230089606
- Publication date Mar 23, 2023
- NVIDIA Corporation
- Vidya Chhabria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Reinforcement driven standard cell placement
- Publication number 20220292335
- Publication date Sep 15, 2022
- NVIDIA Corp.
- Haoxing Ren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FINE-GRAINED PER-VECTOR SCALING FOR NEURAL NETWORK QUANTIZATION
- Publication number 20220067512
- Publication date Mar 3, 2022
- NVIDIA Corporation
- Brucek Kurdo Khailany
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DETERMINING IR DROP
- Publication number 20220067481
- Publication date Mar 3, 2022
- NVIDIA Corporation
- Vidya Chhabria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FINE-GRAINED PER-VECTOR SCALING FOR NEURAL NETWORK QUANTIZATION
- Publication number 20220067530
- Publication date Mar 3, 2022
- NVIDIA Corporation
- Brucek Kurdo Khailany
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STANDARD CELL LAYOUT GENERATION WITH APPLIED ARTIFICIAL INTELLIGENCE
- Publication number 20220027546
- Publication date Jan 27, 2022
- NVIDIA Corp.
- Haoxing Ren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ROUTING CONNECTIONS IN INTEGRATED CIRCUITS BASED ON REINFORCEMENT L...
- Publication number 20210342516
- Publication date Nov 4, 2021
- NVIDIA Corporation
- Haoxing Ren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AVERAGE POWER ESTIMATION USING GRAPH NEURAL NETWORKS
- Publication number 20210158155
- Publication date May 27, 2021
- NVIDIA Corp.
- Yanqing Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT PARASITICS AND DEVICE PARAMETER PREDICTION USING GRAPH NEURA...
- Publication number 20210158127
- Publication date May 27, 2021
- NVIDIA Corp.
- Haoxing Ren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IR DROP PREDICTION WITH MAXIMUM CONVOLUTIONAL NEURAL NETWORK
- Publication number 20200327417
- Publication date Oct 15, 2020
- NVIDIA Corp.
- Zhiyao Xie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Deep Learning Testability Analysis with Graph Convolutional Networks
- Publication number 20200151288
- Publication date May 14, 2020
- NVIDIA Corp.
- Yuzhe Ma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT DESIGN CHANGES USING THROUGH-SILICON VIAS
- Publication number 20190220570
- Publication date Jul 18, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYNTHESIS FOR RANDOM TESTABILITY USING UNREACHABLE STATES IN INTEGR...
- Publication number 20190146031
- Publication date May 16, 2019
- International Business Machines Corporation
- Victor N. Kravets
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LLVM-Based System C Compiler for Architecture Synthesis
- Publication number 20170286079
- Publication date Oct 5, 2017
- Minsik Cho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT DESIGN CHANGES USING THROUGH-SILICON VIAS
- Publication number 20170154148
- Publication date Jun 1, 2017
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING

Haoxing Ren

Person

Patents Grantslast 30 patents

Rail power density aware standard cell placement for integrated cir...

Layout parasitics and device parameter prediction using graph neura...

Standard cell layout generation with applied artificial intelligence

Fine-grained per-vector scaling for neural network quantization

Routing connections in integrated circuits based on reinforcement l...

Rail power density aware standard cell placement for integrated cir...

Layout parasitics and device parameter prediction using graph neura...

IR drop prediction with maximum convolutional neural network

Integrated circuit design changes using through-silicon vias

Deep learning testability analysis with graph convolutional networks

LLVM-based system C compiler for architecture synthesis

Synthesis for random testability using unreachable states in integr...

Integrated circuit design changes using through-silicon vias

Automating a microarchitecture design exploration environment

Through-silicon via access device for integrated circuits

Integrated circuit design changes using through-silicon vias

Placement aware functional engineering change order extraction

Automating a microarchitecture design exploration environment

Integrated circuit design changes using through-silicon vias

Automating a microarchitecture design exploration environment

Through-silicon via access device for integrated circuits

Automating a microarchitecture design exploration environment

Relative ordering circuit synthesis

Automated critical area allocation in a physical synthesized hierar...

Network flow based datapath bit slicing

Soft hierarchy-based physical synthesis for large-scale, high-perfo...

Structured latch and local-clock-buffer planning

Logic modification synthesis for high performance circuits

Logic modification synthesis

Converged large block and structured synthesis for high performance...

Patents Applicationslast 30 patents

AERIAL IMAGE GENERATION THROUGH PHYSICS-INFORMED KERNEL LEARNING

LEARNING-BASED PLACEMENT FOR CONGESTION MITIGATION

DIFFERENTIABLE GLOBAL ROUTER

TRANSFORMER MODEL-BASED CLUSTERING TECHNIQUES FOR STANDARD CELL DES...

PIN DENSITY-BASED CONGESTION ESTIMATION FOR ROUTABILITY-DRIVEN STAN...

DYNAMIC STANDARD CELL EXTERNAL PIN METHODOLOGY FOR ROUTABILITY-DRIV...

RAIL POWER DENSITY AWARE STANDARD CELL PLACEMENT FOR INTEGRATED CIR...

MACHINE LEARNING FOR MASK OPTIMIZATION IN INVERSE LITHOGRAPHY TECHN...

TECHNIQUES FOR GENERATING DESIGNS OF CIRCUITS THAT INCLUDE BUFFERS...

LARGE SCALE MASK OPTIMIZATION WITH CONVOLUTIONAL FOURIER NEURAL OPE...

VLSI PLACEMENT OPTIMIZATION USING SELF-SUPERVISED GRAPH CLUSTERING

GENERATIVE SELF-SUPERVISED LEARNING TO TRANSFORM CIRCUIT NETLISTS

Layout Parasitics and Device Parameter Prediction using Graph Neura...

LITHOGRAPHY SIMULATION USING A NEURAL NETWORK

RAIL POWER DENSITY AWARE STANDARD CELL PLACEMENT FOR INTEGRATED CIR...

REDUCING CROSSTALK PESSIMISM USING GPU-ACCELERATED GATE SIMULATION...

Reinforcement driven standard cell placement

FINE-GRAINED PER-VECTOR SCALING FOR NEURAL NETWORK QUANTIZATION

DETERMINING IR DROP

FINE-GRAINED PER-VECTOR SCALING FOR NEURAL NETWORK QUANTIZATION

STANDARD CELL LAYOUT GENERATION WITH APPLIED ARTIFICIAL INTELLIGENCE

ROUTING CONNECTIONS IN INTEGRATED CIRCUITS BASED ON REINFORCEMENT L...

AVERAGE POWER ESTIMATION USING GRAPH NEURAL NETWORKS

LAYOUT PARASITICS AND DEVICE PARAMETER PREDICTION USING GRAPH NEURA...

IR DROP PREDICTION WITH MAXIMUM CONVOLUTIONAL NEURAL NETWORK

Deep Learning Testability Analysis with Graph Convolutional Networks

INTEGRATED CIRCUIT DESIGN CHANGES USING THROUGH-SILICON VIAS

SYNTHESIS FOR RANDOM TESTABILITY USING UNREACHABLE STATES IN INTEGR...

LLVM-Based System C Compiler for Architecture Synthesis

INTEGRATED CIRCUIT DESIGN CHANGES USING THROUGH-SILICON VIAS