Harald D. Folberth

Person

Boeblingen, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Automated design closure with abutted hierarchy
- Patent number 11,080,456
- Issue date Aug 3, 2021
- International Business Machines Corporation
- Michael Kazda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement of vectorized latches in hierarchical integrated circuit...
- Patent number 10,831,965
- Issue date Nov 10, 2020
- International Business Machines Corporation
- Michael Kazda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Constructing staging trees in hierarchical circuit designs
- Patent number 10,616,103
- Issue date Apr 7, 2020
- International Business Machines Corporation
- Harald Folberth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout of large block synthesis blocks in integrated circuits
- Patent number 10,534,884
- Issue date Jan 14, 2020
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout of large block synthesis blocks in integrated circuits
- Patent number 10,417,366
- Issue date Sep 17, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout of large block synthesis blocks in integrated circuits
- Patent number 10,366,191
- Issue date Jul 30, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout of large block synthesis blocks in integrated circuits
- Patent number 10,242,140
- Issue date Mar 26, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout of large block synthesis blocks in integrated circuits
- Patent number 10,235,487
- Issue date Mar 19, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement clustering-based white space reservation
- Patent number 10,223,489
- Issue date Mar 5, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Area sharing between multiple large block synthesis (LBS) blocks
- Patent number 10,169,519
- Issue date Jan 1, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock control trees
- Patent number 10,146,899
- Issue date Dec 4, 2018
- International Business Machines Corporation
- Harald Folberth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Area sharing between multiple large block synthesis (LBS) blocks
- Patent number 9,946,830
- Issue date Apr 17, 2018
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout of large block synthesis blocks in integrated circuits
- Patent number 9,928,329
- Issue date Mar 27, 2018
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout of large block synthesis blocks in integrated circuits
- Patent number 9,910,948
- Issue date Mar 6, 2018
- International Buisiness Machines Corporatoin
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit placement with electro-migration mitigation
- Patent number 9,679,101
- Issue date Jun 13, 2017
- International Business Machines Corporation
- Harald D. Folberth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit placement with electro-migration mitigation
- Patent number 9,536,037
- Issue date Jan 3, 2017
- International Business Machines Corporation
- Harald D. Folberth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit routing based on total negative slack
- Patent number 9,483,601
- Issue date Nov 1, 2016
- International Business Machines Corporation
- Harald D. Folberth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit routing based on total negative slack
- Patent number 9,471,741
- Issue date Oct 18, 2016
- International Business Machines Corporation
- Harald D. Folberth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Path-based congestion reduction in integrated circuit routing
- Patent number 9,384,316
- Issue date Jul 5, 2016
- International Business Machines Corporation
- Harald Folberth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for enabling parallel layout checking of desig...
- Patent number 6,237,128
- Issue date May 22, 2001
- International Business Machines Corporation
- Harald Folberth
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
AUTOMATED DESIGN CLOSURE WITH ABUTTED HIERARCHY
- Publication number 20210165856
- Publication date Jun 3, 2021
- International Business Machines Corporation
- Michael Kazda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONSTRUCTION OF STAGING TREES ON FULLY HIERARCHICAL VLSI CIRCUIT DE...
- Publication number 20200210545
- Publication date Jul 2, 2020
- International Business Machines Corporation
- Sven Peyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS
- Publication number 20190294739
- Publication date Sep 26, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONSTRUCTING STAGING TREES IN HIERARCHICAL CIRCUIT DESIGNS
- Publication number 20190173781
- Publication date Jun 6, 2019
- International Business Machines Corporation
- Harald Folberth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS
- Publication number 20190065635
- Publication date Feb 28, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS
- Publication number 20190065636
- Publication date Feb 28, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AREA SHARING BETWEEN MULTIPLE LARGE BLOCK SYNTHESIS (LBS) BLOCKS
- Publication number 20180189439
- Publication date Jul 5, 2018
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PLACEMENT CLUSTERING-BASED WHITE SPACE RESERVATION
- Publication number 20180150584
- Publication date May 31, 2018
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS
- Publication number 20180101625
- Publication date Apr 12, 2018
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS
- Publication number 20180101626
- Publication date Apr 12, 2018
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AREA SHARING BETWEEN MULTIPLE LARGE BLOCK SYNTHESIS (LBS) BLOCKS
- Publication number 20170351798
- Publication date Dec 7, 2017
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS
- Publication number 20170212969
- Publication date Jul 27, 2017
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS
- Publication number 20170212970
- Publication date Jul 27, 2017
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT ROUTING BASED ON TOTAL NEGATIVE SLACK
- Publication number 20160283638
- Publication date Sep 29, 2016
- International Business Machines Corporation
- Harald D. Folberth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT ROUTING BASED ON TOTAL NEGATIVE SLACK
- Publication number 20160283637
- Publication date Sep 29, 2016
- International Business Machines Corporation
- Harald D. Folberth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT PLACEMENT WITH ELECTRO-MIGRATION MITIGATION
- Publication number 20160267215
- Publication date Sep 15, 2016
- International Business Machines Corporation
- Harald D. Folberth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT PLACEMENT WITH ELECTRO-MIGRATION MITIGATION
- Publication number 20160267211
- Publication date Sep 15, 2016
- International Business Machines Corporation
- Harald D. Folberth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PATH-BASED CONGESTION REDUCTION IN INTEGRATED CIRCUIT ROUTING
- Publication number 20160012172
- Publication date Jan 14, 2016
- International Business Machines Corporation
- Harald Folberth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Device For Supplying Power to a Microelectronic Chip
- Publication number 20110109378
- Publication date May 12, 2011
- International Business Machines Corporation
- Thomas Buechner
- G01 - MEASURING TESTING

Harald D. Folberth

Person

Patents Grantslast 30 patents

Automated design closure with abutted hierarchy

Placement of vectorized latches in hierarchical integrated circuit...

Constructing staging trees in hierarchical circuit designs

Layout of large block synthesis blocks in integrated circuits

Layout of large block synthesis blocks in integrated circuits

Layout of large block synthesis blocks in integrated circuits

Layout of large block synthesis blocks in integrated circuits

Layout of large block synthesis blocks in integrated circuits

Placement clustering-based white space reservation

Area sharing between multiple large block synthesis (LBS) blocks

Clock control trees

Area sharing between multiple large block synthesis (LBS) blocks

Layout of large block synthesis blocks in integrated circuits

Layout of large block synthesis blocks in integrated circuits

Circuit placement with electro-migration mitigation

Circuit placement with electro-migration mitigation

Circuit routing based on total negative slack

Circuit routing based on total negative slack

Path-based congestion reduction in integrated circuit routing

Method and apparatus for enabling parallel layout checking of desig...

Patents Applicationslast 30 patents

AUTOMATED DESIGN CLOSURE WITH ABUTTED HIERARCHY

CONSTRUCTION OF STAGING TREES ON FULLY HIERARCHICAL VLSI CIRCUIT DE...

LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS

CONSTRUCTING STAGING TREES IN HIERARCHICAL CIRCUIT DESIGNS

LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS

LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS

AREA SHARING BETWEEN MULTIPLE LARGE BLOCK SYNTHESIS (LBS) BLOCKS

PLACEMENT CLUSTERING-BASED WHITE SPACE RESERVATION

LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS

LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS

AREA SHARING BETWEEN MULTIPLE LARGE BLOCK SYNTHESIS (LBS) BLOCKS

LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS

LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS

CIRCUIT ROUTING BASED ON TOTAL NEGATIVE SLACK

CIRCUIT ROUTING BASED ON TOTAL NEGATIVE SLACK

CIRCUIT PLACEMENT WITH ELECTRO-MIGRATION MITIGATION

CIRCUIT PLACEMENT WITH ELECTRO-MIGRATION MITIGATION

PATH-BASED CONGESTION REDUCTION IN INTEGRATED CIRCUIT ROUTING

Method and Device For Supplying Power to a Microelectronic Chip