Harald Streif

Person

South Burlington, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Power savings for memory with error correction mode
- Patent number 7,840,876
- Issue date Nov 23, 2010
- Qimonda AG
- Andre Sturm
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit and method for suppressing gate induced drain leakage
- Patent number 7,639,066
- Issue date Dec 29, 2009
- Qimonda North America Corp.
- Streif Harald
- G11 - INFORMATION STORAGE
Information Patent Grant
Gate induced drain leakage current reduction by voltage regulation...
- Patent number 7,359,271
- Issue date Apr 15, 2008
- Infineon Technologies AG
- Helmut Schneider
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device with column select being variably delayed
- Patent number 7,149,134
- Issue date Dec 12, 2006
- Infineon Technologies AG
- Harald Streif
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device with column select being variably delayed
- Patent number 7,035,150
- Issue date Apr 25, 2006
- Infineon Technologies AG
- Harald Streif
- G11 - INFORMATION STORAGE
Information Patent Grant
Reference voltage detector for power-on sequence in a memory
- Patent number 6,956,409
- Issue date Oct 18, 2005
- Infineon Technologies AG
- Harald Streif
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Soft error improvement for latches
- Patent number 6,724,676
- Issue date Apr 20, 2004
- Infineon Technologies AG
- Ronny Schneider
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
POWER SAVINGS FOR MEMORY WITH ERROR CORRECTION MODE
- Publication number 20080201626
- Publication date Aug 21, 2008
- QIMONDA NORTH AMERICA CORP.
- Andre Sturm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory including error correction code circuit
- Publication number 20080168331
- Publication date Jul 10, 2008
- Thomas Vogelsang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Circuit and Method for Suppressing Gate Induced Drain Leakage
- Publication number 20080142854
- Publication date Jun 19, 2008
- QIMONDA NORTH AMERICA CORP.
- Harald Streif
- G11 - INFORMATION STORAGE
Information Patent Application
Memory with data clock receiver and command/address clock receiver
- Publication number 20080137470
- Publication date Jun 12, 2008
- Josef Schnell
- G11 - INFORMATION STORAGE
Information Patent Application
Gate induced drain leakage current reduction by voltage regulation...
- Publication number 20070147153
- Publication date Jun 28, 2007
- Helmut Schneider
- G11 - INFORMATION STORAGE
Information Patent Application
Memory device with column select being variably delayed
- Publication number 20060050574
- Publication date Mar 9, 2006
- Harald Streif
- G11 - INFORMATION STORAGE
Information Patent Application
Reference voltage detector for power-on sequence in a memory
- Publication number 20050046451
- Publication date Mar 3, 2005
- Harald Streif
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Memory device with column select being variably delayed
- Publication number 20040088475
- Publication date May 6, 2004
- Infineon Technologies North America Corp.
- Harald Streif
- G11 - INFORMATION STORAGE

Harald Streif

Person

Patents Grantslast 30 patents

Power savings for memory with error correction mode

Circuit and method for suppressing gate induced drain leakage

Gate induced drain leakage current reduction by voltage regulation...

Memory device with column select being variably delayed

Memory device with column select being variably delayed

Reference voltage detector for power-on sequence in a memory

Soft error improvement for latches

Patents Applicationslast 30 patents

POWER SAVINGS FOR MEMORY WITH ERROR CORRECTION MODE

Memory including error correction code circuit

Circuit and Method for Suppressing Gate Induced Drain Leakage

Memory with data clock receiver and command/address clock receiver

Gate induced drain leakage current reduction by voltage regulation...

Memory device with column select being variably delayed

Reference voltage detector for power-on sequence in a memory

Memory device with column select being variably delayed