Harindranath Parameswaran

Person

Uttar Pradesh, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Methods, systems, and articles of manufacture for implementing inte...
- Patent number 9,064,063
- Issue date Jun 23, 2015
- Cadence Design Systems, Inc.
- Henry Yu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for double patterning technology (DPT) odd loop v...
- Patent number 9,026,958
- Issue date May 5, 2015
- Cadence Design Systems, Inc.
- Sanjib Ghosh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for derived layers visualization and debugging
- Patent number 8,839,183
- Issue date Sep 16, 2014
- Cadence Design Systems, Inc.
- Pardeep Juneja
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Accelerated characterization of circuits for within-die process var...
- Patent number 8,813,006
- Issue date Aug 19, 2014
- Cadence Design Systems, Inc.
- Harindranath Parameswaran
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Generation, display, and manipulation of measurements in computer g...
- Patent number 8,711,177
- Issue date Apr 29, 2014
- Cadence Design Systems, Inc.
- Chayan Majumder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods, systems, and computer program product for implementing ele...
- Patent number 8,694,943
- Issue date Apr 8, 2014
- Cadence Design Systems, Inc.
- Henry Yu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Netlist partitioning for characterizing effect of within-die variat...
- Patent number 8,612,199
- Issue date Dec 17, 2013
- Cadence Design Systems, Inc.
- Sachin Shrivastava
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for design rule violation reporting and visual...
- Patent number 8,555,237
- Issue date Oct 8, 2013
- Cadence Design Systems, Inc.
- Pardeep Juneja
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for performing improved timing window analysis
- Patent number 8,086,983
- Issue date Dec 27, 2011
- Cadence Design Systems, Inc.
- Sachin Shrivastava
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND APPARATUS FOR DERIVED LAYERS VISUALIZATION AND DEBUGGING
- Publication number 20140215422
- Publication date Jul 31, 2014
- Cadence Design Systems, Inc.
- Pardeep JUNEJA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR PERFORMING IMPROVED TIMING WINDOW ANALYSIS
- Publication number 20100083202
- Publication date Apr 1, 2010
- Sachin Shrivastava
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Netlist Partitioning for Characterizing Effect of Within-Die Variat...
- Publication number 20090164194
- Publication date Jun 25, 2009
- Sachin Shrivastava
- G06 - COMPUTING CALCULATING COUNTING

Harindranath Parameswaran

Person

Patents Grantslast 30 patents

Methods, systems, and articles of manufacture for implementing inte...

Method and system for double patterning technology (DPT) odd loop v...

Method and apparatus for derived layers visualization and debugging

Accelerated characterization of circuits for within-die process var...

Generation, display, and manipulation of measurements in computer g...

Methods, systems, and computer program product for implementing ele...

Netlist partitioning for characterizing effect of within-die variat...

Method and apparatus for design rule violation reporting and visual...

Method and system for performing improved timing window analysis

Patents Applicationslast 30 patents

METHOD AND APPARATUS FOR DERIVED LAYERS VISUALIZATION AND DEBUGGING

METHOD AND SYSTEM FOR PERFORMING IMPROVED TIMING WINDOW ANALYSIS

Netlist Partitioning for Characterizing Effect of Within-Die Variat...