Harish N. Kotecha

Person

Essex Junction, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method for fabricating high circuit density, self-aligned metal lin...
- Patent number 5,143,820
- Issue date Sep 1, 1992
- International Business Machines Corporation
- Harish N. Kotecha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for providing increased dopant concentration in selected reg...
- Patent number 4,814,290
- Issue date Mar 21, 1989
- International Business Machines Corporation
- Jeffrey R. Barber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multiple ROM data state, read/write memory cell
- Patent number 4,805,142
- Issue date Feb 14, 1989
- International Business Machines Corporation
- Claude L. Bertin
- G11 - INFORMATION STORAGE
Information Patent Grant
Quaternary FET read only memory
- Patent number RE32401
- Issue date Apr 14, 1987
- International Business Machines Corporation
- Kenneth E. Beilstein
- 365 - Static information storage and retrieval
Information Patent Grant
Resistor personalized memory device using a resistive gate fet
- Patent number 4,583,201
- Issue date Apr 15, 1986
- International Business Machines Corporation
- Claude L. Bertin
- G11 - INFORMATION STORAGE
Information Patent Grant
Photoresist lift-off process for fabricating semiconductor devices
- Patent number 4,564,584
- Issue date Jan 14, 1986
- IBM Corporation
- Edward C. Fredericks
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making ROM/PLA semiconductor device by late stage persona...
- Patent number 4,536,944
- Issue date Aug 27, 1985
- International Business Machines Corporation
- Al M. Bracco
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated dynamic RAM and ROS
- Patent number 4,488,265
- Issue date Dec 11, 1984
- IBM Corporation
- Harish N. Kotecha
- G11 - INFORMATION STORAGE
Information Patent Grant
Two carrier dual injector apparatus
- Patent number 4,472,726
- Issue date Sep 18, 1984
- The United States of America as represented by the Secretary of the Air Force
- Donelli J. DiMaria
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-volatile static RAM cell with enhanced conduction insulators
- Patent number 4,399,522
- Issue date Aug 16, 1983
- International Business Machines Corporation
- Harish N. Kotecha
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile RAM cell with enhanced conduction insulators
- Patent number 4,388,704
- Issue date Jun 14, 1983
- International Business Machines Corporation
- Claude L. Bertin
- G11 - INFORMATION STORAGE
Information Patent Grant
Electrically alterable double dense memory
- Patent number 4,380,057
- Issue date Apr 12, 1983
- International Business Machines Corporation
- Harish N. Kotecha
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile dynamic RAM cell
- Patent number 4,363,110
- Issue date Dec 7, 1982
- International Business Machines Corp.
- Howard L. Kalter
- G11 - INFORMATION STORAGE
Information Patent Grant
Process for making a dual implanted drain extension for bucket brig...
- Patent number 4,358,890
- Issue date Nov 16, 1982
- IBM Corporation
- Lawrence G. Heller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three terminal electrically erasable programmable read only memory
- Patent number 4,336,603
- Issue date Jun 22, 1982
- International Business Machines Corp.
- Harish N. Kotecha
- G11 - INFORMATION STORAGE
Information Patent Grant
Low voltage electrically erasable programmable read only memory
- Patent number 4,334,292
- Issue date Jun 8, 1982
- International Business Machines Corp.
- Harish N. Kotecha
- G11 - INFORMATION STORAGE
Information Patent Grant
Simultaneously forming fully implanted DMOS together with enhanceme...
- Patent number 4,329,186
- Issue date May 11, 1982
- IBM Corporation
- Harish N. Kotecha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making a MOSFET device with reduced sensitivity of thresh...
- Patent number 4,276,095
- Issue date Jun 30, 1981
- International Business Machines Corporation
- Kenneth E. Beilstein
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Quaternary FET read only memory
- Patent number 4,202,044
- Issue date May 6, 1980
- International Business Machines Corporation
- Kenneth E. Beilstein
- G11 - INFORMATION STORAGE
Information Patent Grant
Inverter with improved load line characteristic
- Patent number 4,138,782
- Issue date Feb 13, 1979
- International Business Machines Corporation
- Francisco H. De La Moneda
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Two and three mask process for IGFET fabrication
- Patent number 4,102,733
- Issue date Jul 25, 1978
- International Business Machines Corporation
- Francisco H. De La Moneda
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Substrate bias modulation to improve mosfet circuit performance
- Patent number 4,092,548
- Issue date May 30, 1978
- International Business Machines Corporation
- Kenneth Edward Beilstein
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
FET inverter with isolated substrate load
- Patent number 4,072,868
- Issue date Feb 7, 1978
- International Business Machines Corporation
- Francisco H. De La Moneda
- H03 - BASIC ELECTRONIC CIRCUITRY

Harish N. Kotecha

Person

Patents Grantslast 30 patents

Method for fabricating high circuit density, self-aligned metal lin...

Method for providing increased dopant concentration in selected reg...

Multiple ROM data state, read/write memory cell

Quaternary FET read only memory

Resistor personalized memory device using a resistive gate fet

Photoresist lift-off process for fabricating semiconductor devices

Method of making ROM/PLA semiconductor device by late stage persona...

Integrated dynamic RAM and ROS

Two carrier dual injector apparatus

Non-volatile static RAM cell with enhanced conduction insulators

Non-volatile RAM cell with enhanced conduction insulators

Electrically alterable double dense memory

Non-volatile dynamic RAM cell

Process for making a dual implanted drain extension for bucket brig...

Three terminal electrically erasable programmable read only memory

Low voltage electrically erasable programmable read only memory

Simultaneously forming fully implanted DMOS together with enhanceme...

Method of making a MOSFET device with reduced sensitivity of thresh...

Quaternary FET read only memory

Inverter with improved load line characteristic

Two and three mask process for IGFET fabrication

Substrate bias modulation to improve mosfet circuit performance

FET inverter with isolated substrate load