Harold Pilo

Person

Underhill, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Memory with external clock synchronized operation
- Patent number 12,361,990
- Issue date Jul 15, 2025
- Synopsys, Inc.
- Harold Pilo
- G11 - INFORMATION STORAGE
Information Patent Grant
Interface level-shifter dual-rail memory architecture
- Patent number 12,340,864
- Issue date Jun 24, 2025
- Synopsys, Inc.
- Harold Pilo
- G11 - INFORMATION STORAGE
Information Patent Grant
Reduced circuit area memory device with a half-word memory architec...
- Patent number 12,340,865
- Issue date Jun 24, 2025
- Synopsys, Inc.
- Harold Pilo
- G11 - INFORMATION STORAGE
Information Patent Grant
Pseudo-2-port memory with dual pre-charge circuits
- Patent number 12,308,091
- Issue date May 20, 2025
- Synopsys, Inc.
- Harold Pilo
- G11 - INFORMATION STORAGE
Information Patent Grant
Output driver level-shifting latch circuit for dual-rail memory
- Patent number 12,243,581
- Issue date Mar 4, 2025
- Synopsys, Inc.
- Harold Pilo
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM non-clamping write driver with write assist
- Patent number 12,165,738
- Issue date Dec 10, 2024
- Synopsys, Inc.
- Harold Pilo
- G11 - INFORMATION STORAGE
Information Patent Grant
At-speed synchronous write-through operation for testing two-port m...
- Patent number 12,148,490
- Issue date Nov 19, 2024
- Synopsys, Inc.
- Harold Pilo
- G11 - INFORMATION STORAGE
Information Patent Grant
Scan chain compression for testing memory of a system on a chip
- Patent number 12,112,818
- Issue date Oct 8, 2024
- Synopsys, Inc.
- Harold Pilo
- G11 - INFORMATION STORAGE
Information Patent Grant
Power supply tracking circuitry for embedded memories
- Patent number 12,094,513
- Issue date Sep 17, 2024
- Synopsys, Inc.
- Harold Pilo
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory clock level-shifting buffer with extended range
- Patent number 12,073,876
- Issue date Aug 27, 2024
- Synopsys, Inc.
- Harold Pilo
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory bypass function for a memory
- Patent number 11,017,873
- Issue date May 25, 2021
- Synopsys, Inc.
- John Edward Barth
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for memory noise-free wake-up protocol from po...
- Patent number 10,971,218
- Issue date Apr 6, 2021
- Synopsys, Inc.
- Harold Pilo
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for integrated level-shifter and memory clock
- Patent number 10,706,916
- Issue date Jul 7, 2020
- Synopsys, Inc.
- Harold Pilo
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory bypass function for a memory
- Patent number 10,650,906
- Issue date May 12, 2020
- Synopsys, Inc.
- John Edward Barth
- G11 - INFORMATION STORAGE
Information Patent Grant
Overvoltage protection for a fine grained negative wordline scheme
- Patent number 10,636,457
- Issue date Apr 28, 2020
- International Business Machines Corporation
- Harold Pilo
- G11 - INFORMATION STORAGE
Information Patent Grant
Overvoltage protection for a fine grained negative wordline scheme
- Patent number 10,381,052
- Issue date Aug 13, 2019
- International Business Machines Corporation
- Harold Pilo
- G11 - INFORMATION STORAGE
Information Patent Grant
Overvoltage protection for a fine grained negative wordline scheme
- Patent number 9,953,698
- Issue date Apr 24, 2018
- International Business Machines Corporation
- Harold Pilo
- G11 - INFORMATION STORAGE
Information Patent Grant
Overvoltage protection for a fine grained negative wordline scheme
- Patent number 9,881,666
- Issue date Jan 30, 2018
- International Business Machines Corporation
- Harold Pilo
- G11 - INFORMATION STORAGE
Information Patent Grant
Overvoltage protection for a fine grained negative wordline scheme
- Patent number 9,734,892
- Issue date Aug 15, 2017
- International Business Machines Corporation
- Harold Pilo
- G11 - INFORMATION STORAGE
Information Patent Grant
Overvoltage protection for a fine grained negative wordline scheme
- Patent number 9,734,891
- Issue date Aug 15, 2017
- International Business Machines Corporation
- Harold Pilo
- G11 - INFORMATION STORAGE
Information Patent Grant
Overvoltage protection for a fine grained negative wordline scheme
- Patent number 9,679,635
- Issue date Jun 13, 2017
- International Business Machines Corporation
- Harold Pilo
- G11 - INFORMATION STORAGE
Information Patent Grant
TCAM field enable logic
- Patent number 9,613,700
- Issue date Apr 4, 2017
- Invecas, Inc.
- Harold Pilo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Deep-sleep wake up for a memory device
- Patent number 9,564,180
- Issue date Feb 7, 2017
- Invecas, Inc.
- Harold Pilo
- G11 - INFORMATION STORAGE
Information Patent Grant
Overvoltage protection for a fine grained negative wordline scheme
- Patent number 9,318,162
- Issue date Apr 19, 2016
- International Business Machines Corporation
- Harold Pilo
- G11 - INFORMATION STORAGE
Information Patent Grant
Regulated power gating for growable memory
- Patent number 9,311,978
- Issue date Apr 12, 2016
- GLOBALFOUNDRIES Inc.
- Harold Pilo
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM circuit with increased write margin
- Patent number 9,230,637
- Issue date Jan 5, 2016
- GLOBALFOUNDRIES Inc.
- Shahid Ahmad Butt
- G11 - INFORMATION STORAGE
Information Patent Grant
Fine granularity power gating
- Patent number 9,183,906
- Issue date Nov 10, 2015
- International Business Machines Corporation
- Chad A. Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM write-assisted operation with VDD-to-VCS level shifting
- Patent number 9,123,439
- Issue date Sep 1, 2015
- International Business Machines Corporation
- Harold Pilo
- G11 - INFORMATION STORAGE
Information Patent Grant
Leakage-aware voltage regulation circuit and method
- Patent number 9,058,046
- Issue date Jun 16, 2015
- International Business Machines Corporation
- Harold Pilo
- G05 - CONTROLLING REGULATING
Information Patent Grant
Vdiff max limiter in SRAMs for improved yield and power
- Patent number 8,654,594
- Issue date Feb 18, 2014
- International Business Machines Corporation
- Igor Arsovski
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
REDUCED CIRCUIT AREA MEMORY DEVICE WITH A HALF-WORD MEMORY ARCHITEC...
- Publication number 20240371416
- Publication date Nov 7, 2024
- Synopsys, Inc.
- Harold PILO
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CLOCK LEVEL-SHIFTING BUFFER WITH EXTENDED RANGE
- Publication number 20240062810
- Publication date Feb 22, 2024
- Synopsys, Inc.
- Harold Pilo
- G11 - INFORMATION STORAGE
Information Patent Application
INTERFACE LEVEL-SHIFTER DUAL-RAIL MEMORY ARCHITECTURE
- Publication number 20230260555
- Publication date Aug 17, 2023
- Synopsys, Inc.
- Harold PILO
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM Non-Clamping Write Driver with Write Assist
- Publication number 20230206970
- Publication date Jun 29, 2023
- Synopsys, Inc.
- Harold Pilo
- G11 - INFORMATION STORAGE
Information Patent Application
POWER SUPPLY TRACKING CIRCUITRY FOR EMBEDDED MEMORIES
- Publication number 20230125268
- Publication date Apr 27, 2023
- Synopsys, Inc.
- Harold PILO
- G11 - INFORMATION STORAGE
Information Patent Application
SCAN CHAIN COMPRESSION FOR TESTING MEMORY OF A SYSTEM ON A CHIP
- Publication number 20230005562
- Publication date Jan 5, 2023
- Synopsys, Inc.
- Harold PILO
- G11 - INFORMATION STORAGE
Information Patent Application
PSEUDO-2-PORT MEMORY WITH DUAL PRE-CHARGE CIRCUITS
- Publication number 20220208239
- Publication date Jun 30, 2022
- Synopsys, Inc.
- Harold PILO
- G11 - INFORMATION STORAGE
Information Patent Application
Method and Apparatus for Memory Noise-Free Wake-Up Protocol from Po...
- Publication number 20200381042
- Publication date Dec 3, 2020
- Synopsys, Inc.
- Harold Pilo
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Bypass Function For A Memory
- Publication number 20200234784
- Publication date Jul 23, 2020
- Synopsys, Inc.
- John Edward Barth
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Bypass Function For A Memory
- Publication number 20200051658
- Publication date Feb 13, 2020
- Invecas, Inc.
- John Edward Barth
- G11 - INFORMATION STORAGE
Information Patent Application
OVERVOLTAGE PROTECTION FOR A FINE GRAINED NEGATIVE WORDLINE SCHEME
- Publication number 20190259427
- Publication date Aug 22, 2019
- International Business Machines Corporation
- Harold PILO
- G11 - INFORMATION STORAGE
Information Patent Application
OVERVOLTAGE PROTECTION FOR A FINE GRAINED NEGATIVE WORDLINE SCHEME
- Publication number 20180174645
- Publication date Jun 21, 2018
- International Business Machines Corporation
- Harold PILO
- G11 - INFORMATION STORAGE
Information Patent Application
OVERVOLTAGE PROTECTION FOR A FINE GRAINED NEGATIVE WORDLINE SCHEME
- Publication number 20180068711
- Publication date Mar 8, 2018
- International Business Machines Corporation
- Harold PILO
- G11 - INFORMATION STORAGE
Information Patent Application
OVERVOLTAGE PROTECTION FOR A FINE GRAINED NEGATIVE WORDLINE SCHEME
- Publication number 20160093360
- Publication date Mar 31, 2016
- International Business Machines Corporation
- Harold PILO
- G11 - INFORMATION STORAGE
Information Patent Application
OVERVOLTAGE PROTECTION FOR A FINE GRAINED NEGATIVE WORDLINE SCHEME
- Publication number 20160093361
- Publication date Mar 31, 2016
- International Business Machines Corporation
- Harold PILO
- G11 - INFORMATION STORAGE
Information Patent Application
OVERVOLTAGE PROTECTION FOR A FINE GRAINED NEGATIVE WORDLINE SCHEME
- Publication number 20160093359
- Publication date Mar 31, 2016
- International Business Machines Corporation
- Harold PILO
- G11 - INFORMATION STORAGE
Information Patent Application
OVERVOLTAGE PROTECTION FOR A FINE GRAINED NEGATIVE WORDLINE SCHEME
- Publication number 20160086658
- Publication date Mar 24, 2016
- International Business Machines Corporation
- Harold PILO
- G11 - INFORMATION STORAGE
Information Patent Application
OVERVOLTAGE PROTECTION FOR A FINE GRAINED NEGATIVE WORDLINE SCHEME
- Publication number 20160035397
- Publication date Feb 4, 2016
- International Business Machines Corporation
- Harold PILO
- G11 - INFORMATION STORAGE
Information Patent Application
LEAKAGE-AWARE VOLTAGE REGULATION CIRCUIT AND METHOD
- Publication number 20150168982
- Publication date Jun 18, 2015
- International Business Machines Corporation
- Harold PILO
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM WRITE-ASSISTED OPERATION WITH VDD-TO-VCS LEVEL SHIFTING
- Publication number 20150146479
- Publication date May 28, 2015
- International Business Machines Corporation
- Harold Pilo
- G11 - INFORMATION STORAGE
Information Patent Application
REGULATED POWER GATING FOR GROWABLE MEMORY
- Publication number 20150109873
- Publication date Apr 23, 2015
- International Business Machines Corporation
- Harold PILO
- G11 - INFORMATION STORAGE
Information Patent Application
FINE GRANULARITY POWER GATING
- Publication number 20140092700
- Publication date Apr 3, 2014
- International Business Machines Corporation
- Chad A. Adams
- G11 - INFORMATION STORAGE
Information Patent Application
VDIFF MAX LIMITER IN SRAMS FOR IMPROVED YIELD AND POWER
- Publication number 20130223161
- Publication date Aug 29, 2013
- International Business Machines Corporation
- Igor Arsovski
- G11 - INFORMATION STORAGE
Information Patent Application
FINE GRANULARITY POWER GATING
- Publication number 20130148455
- Publication date Jun 13, 2013
- International Business Machines Corporation
- Robert M. Houle
- G11 - INFORMATION STORAGE
Information Patent Application
DUAL POWER SUPPLY MEMORY ARRAY HAVING A CONTROL CIRCUIT THAT DYANMI...
- Publication number 20130135944
- Publication date May 30, 2013
- International Business Machines Corporation
- George M. Braceras
- G11 - INFORMATION STORAGE
Information Patent Application
DEVICE AND METHOD FOR DETECTING RESISTIVE DEFECT
- Publication number 20130033948
- Publication date Feb 7, 2013
- International Business Machines Corporation
- George Maria Braceras
- G11 - INFORMATION STORAGE
Information Patent Application
STATIC RANDOM ACCESS MEMORY (SRAM) WRITE ASSIST CIRCUIT WITH LEAKAG...
- Publication number 20120140551
- Publication date Jun 7, 2012
- International Business Machines Corporation
- Igor Arsovski
- G11 - INFORMATION STORAGE
Information Patent Application
WORD-LINE LEVEL SHIFT CIRCUIT
- Publication number 20120134221
- Publication date May 31, 2012
- International Business Machines Corporation
- Igor Arsovski
- G11 - INFORMATION STORAGE
Information Patent Application
Methods and Systems for Adjusting Wordline Up-Level Voltage to Impr...
- Publication number 20120075919
- Publication date Mar 29, 2012
- International Business Machines Corporation
- Igor Arsovski
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM Having Wordline Up-Level Voltage Adjustable to Assist Bitcell...
- Publication number 20120075918
- Publication date Mar 29, 2012
- International Business Machines Corporation
- Igor Arsovski
- G11 - INFORMATION STORAGE

Harold Pilo

Person

Patents Grantslast 30 patents

Memory with external clock synchronized operation

Interface level-shifter dual-rail memory architecture

Reduced circuit area memory device with a half-word memory architec...

Pseudo-2-port memory with dual pre-charge circuits

Output driver level-shifting latch circuit for dual-rail memory

SRAM non-clamping write driver with write assist

At-speed synchronous write-through operation for testing two-port m...

Scan chain compression for testing memory of a system on a chip

Power supply tracking circuitry for embedded memories

Memory clock level-shifting buffer with extended range

Memory bypass function for a memory

Method and apparatus for memory noise-free wake-up protocol from po...

Method and apparatus for integrated level-shifter and memory clock

Memory bypass function for a memory

Overvoltage protection for a fine grained negative wordline scheme

Overvoltage protection for a fine grained negative wordline scheme

Overvoltage protection for a fine grained negative wordline scheme

Overvoltage protection for a fine grained negative wordline scheme

Overvoltage protection for a fine grained negative wordline scheme

Overvoltage protection for a fine grained negative wordline scheme

Overvoltage protection for a fine grained negative wordline scheme

TCAM field enable logic

Deep-sleep wake up for a memory device

Overvoltage protection for a fine grained negative wordline scheme

Regulated power gating for growable memory

SRAM circuit with increased write margin

Fine granularity power gating

SRAM write-assisted operation with VDD-to-VCS level shifting

Leakage-aware voltage regulation circuit and method

Vdiff max limiter in SRAMs for improved yield and power

Patents Applicationslast 30 patents

REDUCED CIRCUIT AREA MEMORY DEVICE WITH A HALF-WORD MEMORY ARCHITEC...

MEMORY CLOCK LEVEL-SHIFTING BUFFER WITH EXTENDED RANGE

INTERFACE LEVEL-SHIFTER DUAL-RAIL MEMORY ARCHITECTURE

SRAM Non-Clamping Write Driver with Write Assist

POWER SUPPLY TRACKING CIRCUITRY FOR EMBEDDED MEMORIES

SCAN CHAIN COMPRESSION FOR TESTING MEMORY OF A SYSTEM ON A CHIP

PSEUDO-2-PORT MEMORY WITH DUAL PRE-CHARGE CIRCUITS

Method and Apparatus for Memory Noise-Free Wake-Up Protocol from Po...

Memory Bypass Function For A Memory

Memory Bypass Function For A Memory

OVERVOLTAGE PROTECTION FOR A FINE GRAINED NEGATIVE WORDLINE SCHEME

OVERVOLTAGE PROTECTION FOR A FINE GRAINED NEGATIVE WORDLINE SCHEME

OVERVOLTAGE PROTECTION FOR A FINE GRAINED NEGATIVE WORDLINE SCHEME

OVERVOLTAGE PROTECTION FOR A FINE GRAINED NEGATIVE WORDLINE SCHEME

OVERVOLTAGE PROTECTION FOR A FINE GRAINED NEGATIVE WORDLINE SCHEME

OVERVOLTAGE PROTECTION FOR A FINE GRAINED NEGATIVE WORDLINE SCHEME

OVERVOLTAGE PROTECTION FOR A FINE GRAINED NEGATIVE WORDLINE SCHEME

OVERVOLTAGE PROTECTION FOR A FINE GRAINED NEGATIVE WORDLINE SCHEME

LEAKAGE-AWARE VOLTAGE REGULATION CIRCUIT AND METHOD

SRAM WRITE-ASSISTED OPERATION WITH VDD-TO-VCS LEVEL SHIFTING

REGULATED POWER GATING FOR GROWABLE MEMORY

FINE GRANULARITY POWER GATING

VDIFF MAX LIMITER IN SRAMS FOR IMPROVED YIELD AND POWER

FINE GRANULARITY POWER GATING

DUAL POWER SUPPLY MEMORY ARRAY HAVING A CONTROL CIRCUIT THAT DYANMI...

DEVICE AND METHOD FOR DETECTING RESISTIVE DEFECT

STATIC RANDOM ACCESS MEMORY (SRAM) WRITE ASSIST CIRCUIT WITH LEAKAG...

WORD-LINE LEVEL SHIFT CIRCUIT

Methods and Systems for Adjusting Wordline Up-Level Voltage to Impr...

SRAM Having Wordline Up-Level Voltage Adjustable to Assist Bitcell...