Harry Barowski

Person

Boeblingen, DE

People

Patents Grantslast 30 patents

Information Patent Grant
True complement dynamic circuit and method for combining binary data
- Patent number 11,881,853
- Issue date Jan 23, 2024
- International Business Machines Corporation
- Michael Berthold Kugel
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Erasing a partition of an SRAM array with hardware support
- Patent number 11,557,335
- Issue date Jan 17, 2023
- International Business Machines Corporation
- Martin Bernhard Schmidt
- G11 - INFORMATION STORAGE
Information Patent Grant
Qubit tuning by magnetic fields in superconductors
- Patent number 11,501,196
- Issue date Nov 15, 2022
- International Business Machines Corporation
- Albert Frisch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital logic circuit for deterring race violations at an array tes...
- Patent number 11,043,938
- Issue date Jun 22, 2021
- International Business Machines Corporation
- Harry Barowski
- G01 - MEASURING TESTING
Information Patent Grant
RAM memory with pre-charging circuitry coupled to global bit-lines...
- Patent number 10,984,843
- Issue date Apr 20, 2021
- International Business Machines Corporation
- Martin Bernhard Schmidt
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit design changes using through-silicon vias
- Patent number 10,956,644
- Issue date Mar 23, 2021
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Global bit line latch performance and power optimization
- Patent number 10,832,763
- Issue date Nov 10, 2020
- International Business Machines Corporation
- Martin Bernhard Schmidt
- G11 - INFORMATION STORAGE
Information Patent Grant
Testing content addressable memory and random access memory
- Patent number 10,593,420
- Issue date Mar 17, 2020
- International Business Machines Corporation
- Harry Barowski
- G11 - INFORMATION STORAGE
Information Patent Grant
Digital logic circuit for deterring race violations at an array tes...
- Patent number 10,587,248
- Issue date Mar 10, 2020
- International Business Machines Corporation
- Harry Barowski
- G11 - INFORMATION STORAGE
Information Patent Grant
Layout of large block synthesis blocks in integrated circuits
- Patent number 10,534,884
- Issue date Jan 14, 2020
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout of large block synthesis blocks in integrated circuits
- Patent number 10,417,366
- Issue date Sep 17, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital logic circuit for deterring race violations at an array tes...
- Patent number 10,367,481
- Issue date Jul 30, 2019
- International Business Machines Corporation
- Harry Barowski
- G01 - MEASURING TESTING
Information Patent Grant
Layout of large block synthesis blocks in integrated circuits
- Patent number 10,366,191
- Issue date Jul 30, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cross bar switch structure for highly congested environments
- Patent number 10,333,508
- Issue date Jun 25, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout of large block synthesis blocks in integrated circuits
- Patent number 10,242,140
- Issue date Mar 26, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout of large block synthesis blocks in integrated circuits
- Patent number 10,235,487
- Issue date Mar 19, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement clustering-based white space reservation
- Patent number 10,223,489
- Issue date Mar 5, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit design changes using through-silicon vias
- Patent number 10,223,491
- Issue date Mar 5, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Area sharing between multiple large block synthesis (LBS) blocks
- Patent number 10,169,519
- Issue date Jan 1, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Testing content addressable memory and random access memory
- Patent number 10,170,199
- Issue date Jan 1, 2019
- International Business Machines Corporation
- Harry Barowski
- G11 - INFORMATION STORAGE
Information Patent Grant
Testing content addressable memory and random access memory
- Patent number 10,079,070
- Issue date Sep 18, 2018
- International Business Machines Corporation
- Harry Barowski
- G11 - INFORMATION STORAGE
Information Patent Grant
Area sharing between multiple large block synthesis (LBS) blocks
- Patent number 9,946,830
- Issue date Apr 17, 2018
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout of large block synthesis blocks in integrated circuits
- Patent number 9,928,329
- Issue date Mar 27, 2018
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout of large block synthesis blocks in integrated circuits
- Patent number 9,910,948
- Issue date Mar 6, 2018
- International Buisiness Machines Corporatoin
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pipelining out-of-order instructions
- Patent number 9,733,945
- Issue date Aug 15, 2017
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
De-coupling capacitance placement
- Patent number 9,684,759
- Issue date Jun 20, 2017
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
De-coupling capacitance placement
- Patent number 9,679,099
- Issue date Jun 13, 2017
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for increasing instruction issue rate and reducing laten...
- Patent number 9,658,853
- Issue date May 23, 2017
- GLOBALFOUNDRIES Inc.
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Through-silicon via access device for integrated circuits
- Patent number 9,633,928
- Issue date Apr 25, 2017
- International Business Machines Corporation
- Harry Barowski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit design changes using through-silicon vias
- Patent number 9,569,580
- Issue date Feb 14, 2017
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
TRUE COMPLEMENT DYNAMIC CIRCUIT AND METHOD FOR COMBINING BINARY DATA
- Publication number 20230060610
- Publication date Mar 2, 2023
- International Business Machines Corporation
- Michael Berthold Kugel
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ERASING A PARTITION OF AN SRAM ARRAY WITH HARDWARE SUPPORT
- Publication number 20220013166
- Publication date Jan 13, 2022
- International Business Machines Corporation
- Martin Bernhard Schmidt
- G11 - INFORMATION STORAGE
Information Patent Application
REDUCING MEMORY POWER CONSUMPTION
- Publication number 20200279593
- Publication date Sep 3, 2020
- International Business Machines Corporation
- Martin Bernhard Schmidt
- G11 - INFORMATION STORAGE
Information Patent Application
GLOBAL BIT LINE LATCH PERFORMANCE AND POWER OPTIMIZATION
- Publication number 20200194060
- Publication date Jun 18, 2020
- International Business Machines Corporation
- Martin Bernhard Schmidt
- G11 - INFORMATION STORAGE
Information Patent Application
QUBIT TUNING BY MAGNETIC FIELDS IN SUPERCONDUCTORS
- Publication number 20200167684
- Publication date May 28, 2020
- International Business Machines Corporation
- Albert Frisch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
QUBIT TUNING BY MAGNETIC FIELDS IN SUPERCONDUCTORS
- Publication number 20200167683
- Publication date May 28, 2020
- International Business Machines Corporation
- Albert Frisch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIGITAL LOGIC CIRCUIT FOR DETERRING RACE VIOLATIONS AT AN ARRAY TES...
- Publication number 20200127649
- Publication date Apr 23, 2020
- International Business Machines Corporation
- Harry Barowski
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS
- Publication number 20190294739
- Publication date Sep 26, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT DESIGN CHANGES USING THROUGH-SILICON VIAS
- Publication number 20190220570
- Publication date Jul 18, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS
- Publication number 20190065635
- Publication date Feb 28, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS
- Publication number 20190065636
- Publication date Feb 28, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CROSS BAR SWITCH STRUCTURE FOR HIGHLY CONGESTED ENVIRONMENTS
- Publication number 20180287598
- Publication date Oct 4, 2018
- International Business Machines Corporation
- Harry BAROWSKI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIGITAL LOGIC CIRCUIT
- Publication number 20180212594
- Publication date Jul 26, 2018
- International Business Machines Corporation
- Harry Barowski
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DIGITAL LOGIC CIRCUIT
- Publication number 20180212595
- Publication date Jul 26, 2018
- International Business Machines Corporation
- Harry Barowski
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
AREA SHARING BETWEEN MULTIPLE LARGE BLOCK SYNTHESIS (LBS) BLOCKS
- Publication number 20180189439
- Publication date Jul 5, 2018
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TESTING CONTENT ADDRESSABLE MEMORY AND RANDOM ACCESS MEMORY
- Publication number 20180174666
- Publication date Jun 21, 2018
- International Business Machines Corporation
- Harry Barowski
- G11 - INFORMATION STORAGE
Information Patent Application
PLACEMENT CLUSTERING-BASED WHITE SPACE RESERVATION
- Publication number 20180150584
- Publication date May 31, 2018
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TESTING CONTENT ADDRESSABLE MEMORY AND RANDOM ACCESS MEMORY
- Publication number 20180151248
- Publication date May 31, 2018
- International Business Machines Corporation
- Harry Barowski
- G11 - INFORMATION STORAGE
Information Patent Application
TESTING CONTENT ADDRESSABLE MEMORY AND RANDOM ACCESS MEMORY
- Publication number 20180114585
- Publication date Apr 26, 2018
- International Business Machines Corporation
- Harry Barowski
- G11 - INFORMATION STORAGE
Information Patent Application
LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS
- Publication number 20180101625
- Publication date Apr 12, 2018
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS
- Publication number 20180101626
- Publication date Apr 12, 2018
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AREA SHARING BETWEEN MULTIPLE LARGE BLOCK SYNTHESIS (LBS) BLOCKS
- Publication number 20170351798
- Publication date Dec 7, 2017
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS
- Publication number 20170212969
- Publication date Jul 27, 2017
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS
- Publication number 20170212970
- Publication date Jul 27, 2017
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT DESIGN CHANGES USING THROUGH-SILICON VIAS
- Publication number 20170154148
- Publication date Jun 1, 2017
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DE-COUPLING CAPACITANCE PLACEMENT
- Publication number 20170004248
- Publication date Jan 5, 2017
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DE-COUPLING CAPACITANCE PLACEMENT
- Publication number 20170004239
- Publication date Jan 5, 2017
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PIPELINING OUT-OF-ORDER INSTRUCTIONS
- Publication number 20160179551
- Publication date Jun 23, 2016
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT DESIGN CHANGES USING THROUGH-SILICON VIAS
- Publication number 20160070842
- Publication date Mar 10, 2016
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THROUGH-SILICON VIA ACCESS DEVICE FOR INTEGRATED CIRCUITS
- Publication number 20160071786
- Publication date Mar 10, 2016
- International Business Machines Corporation
- Harry Barowski
- H01 - BASIC ELECTRIC ELEMENTS

Harry Barowski

Person

Patents Grantslast 30 patents

True complement dynamic circuit and method for combining binary data

Erasing a partition of an SRAM array with hardware support

Qubit tuning by magnetic fields in superconductors

Digital logic circuit for deterring race violations at an array tes...

RAM memory with pre-charging circuitry coupled to global bit-lines...

Integrated circuit design changes using through-silicon vias

Global bit line latch performance and power optimization

Testing content addressable memory and random access memory

Digital logic circuit for deterring race violations at an array tes...

Layout of large block synthesis blocks in integrated circuits

Layout of large block synthesis blocks in integrated circuits

Digital logic circuit for deterring race violations at an array tes...

Layout of large block synthesis blocks in integrated circuits

Cross bar switch structure for highly congested environments

Layout of large block synthesis blocks in integrated circuits

Layout of large block synthesis blocks in integrated circuits

Placement clustering-based white space reservation

Integrated circuit design changes using through-silicon vias

Area sharing between multiple large block synthesis (LBS) blocks

Testing content addressable memory and random access memory

Testing content addressable memory and random access memory

Area sharing between multiple large block synthesis (LBS) blocks

Layout of large block synthesis blocks in integrated circuits

Layout of large block synthesis blocks in integrated circuits

Pipelining out-of-order instructions

De-coupling capacitance placement

De-coupling capacitance placement

Techniques for increasing instruction issue rate and reducing laten...

Through-silicon via access device for integrated circuits

Integrated circuit design changes using through-silicon vias

Patents Applicationslast 30 patents

TRUE COMPLEMENT DYNAMIC CIRCUIT AND METHOD FOR COMBINING BINARY DATA

ERASING A PARTITION OF AN SRAM ARRAY WITH HARDWARE SUPPORT

REDUCING MEMORY POWER CONSUMPTION

GLOBAL BIT LINE LATCH PERFORMANCE AND POWER OPTIMIZATION

QUBIT TUNING BY MAGNETIC FIELDS IN SUPERCONDUCTORS

QUBIT TUNING BY MAGNETIC FIELDS IN SUPERCONDUCTORS

DIGITAL LOGIC CIRCUIT FOR DETERRING RACE VIOLATIONS AT AN ARRAY TES...

LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS

INTEGRATED CIRCUIT DESIGN CHANGES USING THROUGH-SILICON VIAS

LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS

LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS

CROSS BAR SWITCH STRUCTURE FOR HIGHLY CONGESTED ENVIRONMENTS

DIGITAL LOGIC CIRCUIT

DIGITAL LOGIC CIRCUIT

AREA SHARING BETWEEN MULTIPLE LARGE BLOCK SYNTHESIS (LBS) BLOCKS

TESTING CONTENT ADDRESSABLE MEMORY AND RANDOM ACCESS MEMORY

PLACEMENT CLUSTERING-BASED WHITE SPACE RESERVATION

TESTING CONTENT ADDRESSABLE MEMORY AND RANDOM ACCESS MEMORY

TESTING CONTENT ADDRESSABLE MEMORY AND RANDOM ACCESS MEMORY

LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS

LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS

AREA SHARING BETWEEN MULTIPLE LARGE BLOCK SYNTHESIS (LBS) BLOCKS

LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS

LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS

INTEGRATED CIRCUIT DESIGN CHANGES USING THROUGH-SILICON VIAS

DE-COUPLING CAPACITANCE PLACEMENT

DE-COUPLING CAPACITANCE PLACEMENT

PIPELINING OUT-OF-ORDER INSTRUCTIONS

INTEGRATED CIRCUIT DESIGN CHANGES USING THROUGH-SILICON VIAS

THROUGH-SILICON VIA ACCESS DEVICE FOR INTEGRATED CIRCUITS