Harry H. Kuo

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San Jose, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
High speed zero DC power programmable logic device (PLD) architecture
- Patent number 6,809,550
- Issue date Oct 26, 2004
- Atmel Corporation
- Saroj Pathak
- G11 - INFORMATION STORAGE
Information Patent Grant
Power-on reset circuit
- Patent number 6,744,291
- Issue date Jun 1, 2004
- Atmel Corporation
- James E. Payne
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High voltage bit/column latch for Vcc operation
- Patent number 6,618,289
- Issue date Sep 9, 2003
- Atmel Corporation
- Saroj Pathak
- G11 - INFORMATION STORAGE
Information Patent Grant
Secure programmable logic device
- Patent number 6,331,784
- Issue date Dec 18, 2001
- Atmel Corporation
- Martin T. Mason
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low power voltage regulator circuit for use in an integrated circui...
- Patent number 6,320,454
- Issue date Nov 20, 2001
- Atmel Corporation
- Saroj Pathak
- G05 - CONTROLLING REGULATING

Patents Applicationslast 30 patents

Information Patent Application
High speed zero DC power programmable logic device (PLD) architecture
- Publication number 20040056679
- Publication date Mar 25, 2004
- Saroj Pathak
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Power-on reset circuit
- Publication number 20040041601
- Publication date Mar 4, 2004
- James E. Payne
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
High voltage bit/column latch for Vcc operation
- Publication number 20030081448
- Publication date May 1, 2003
- Saroj Pathak
- G11 - INFORMATION STORAGE