Harsh Dev Sharma

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
On-chip measurement of signal state duration
- Patent number 7,131,034
- Issue date Oct 31, 2006
- Sun Microsystems, Inc.
- Nadeem N. Eleyan
- G01 - MEASURING TESTING
Information Patent Grant
Intelligent delay insertion based on transition
- Patent number 7,116,126
- Issue date Oct 3, 2006
- Sun Microsystems, Inc.
- Nayon Tomsio
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
On-chip signal state duration measurement and adjustment
- Patent number 7,036,098
- Issue date Apr 25, 2006
- Sun Microsystems, Inc.
- Nadeem N. Eleyan
- G01 - MEASURING TESTING
Information Patent Grant
Pulsed dynamic keeper gating
- Patent number 7,034,576
- Issue date Apr 25, 2006
- Sun Microsystems, Inc.
- Howard Levy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Priority delay insertion circuit
- Patent number 7,016,422
- Issue date Mar 21, 2006
- Sun Microsystems, Inc.
- Harsh D. Sharma
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
On-chip PLL locked frequency determination method and system
- Patent number 6,891,403
- Issue date May 10, 2005
- Sun Microsystems, Inc.
- Harsh D. Sharma
- G01 - MEASURING TESTING
Information Patent Grant
Dividing and distributing the drive strength of a single clock buffer
- Patent number 6,819,138
- Issue date Nov 16, 2004
- Sun Microsystems, Inc.
- David Hogenmiller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Use of coupling capacitance to balance skew in a network
- Patent number 6,789,245
- Issue date Sep 7, 2004
- Sun Microsystems, Inc.
- Shervin Hojat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and a system to distribute clock signals in digital circuits
- Patent number 6,737,902
- Issue date May 18, 2004
- Sun Microsystems, Inc.
- Nayon Tomsio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, system and computer product to translate electronic schemat...
- Patent number 6,684,372
- Issue date Jan 27, 2004
- Sun Microsystems, Inc.
- Sze Tom
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Domino to static circuit technique
- Patent number 6,208,907
- Issue date Mar 27, 2001
- International Business Machines Corporation
- Christopher McCall Durham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for controlling delays in silicon on insulator circuits
- Patent number 6,111,455
- Issue date Aug 29, 2000
- International Business Machines Corporation
- Nadeem Eleyan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and device for the reduction of latch insertion delay
- Patent number 6,107,852
- Issue date Aug 22, 2000
- International Business Machines Corporation
- Christopher McCall Durham
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Reduced power dynamic logic circuit that inhibits reevaluation of s...
- Patent number 6,037,804
- Issue date Mar 14, 2000
- International Business Machines Corporation
- Christopher McCall Durham
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
On-chip signal state duration measurement and adjustment
- Publication number 20040268280
- Publication date Dec 30, 2004
- Nadeem N. Eleyan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Pulsed dynamic keeper gating
- Publication number 20040263208
- Publication date Dec 30, 2004
- Sun Microsystems, Inc.
- Howard Levy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
On-chip measurement of signal state duration
- Publication number 20040093535
- Publication date May 13, 2004
- Nadeem N. Eleyan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Dividing and distributing the drive strength of a single clock buffer
- Publication number 20040085094
- Publication date May 6, 2004
- Sun Microsystems, Inc.
- David Hogenmiller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Template based clock routing and balancing
- Publication number 20040078773
- Publication date Apr 22, 2004
- Sun Microsystems, Inc.
- Harsh Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
On-chip PLL locked frequency determination method and system
- Publication number 20040075477
- Publication date Apr 22, 2004
- Sun Microsystems, Inc.
- Harsh D. Sharma
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Use of coupling capacitance to balance skew in a network
- Publication number 20040068709
- Publication date Apr 8, 2004
- Sun Microsystems, Inc.
- Shervin Hojat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and a system to distribute clock signals in digital circuits
- Publication number 20030214340
- Publication date Nov 20, 2003
- SUN MICROSYSTEMS, INC.
- Nayon Tomsio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method, system and computer product to translate electronic schemat...
- Publication number 20030177456
- Publication date Sep 18, 2003
- SUN MICROSYSTEMS, INC.
- Sze Tom
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Zero-skew transition detection circuit
- Publication number 20030120982
- Publication date Jun 26, 2003
- Howard L. Levy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Intelligent delay insertion based on transition
- Publication number 20030072332
- Publication date Apr 17, 2003
- Nayon Tomsio
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Priority delay insertion circuit
- Publication number 20030031194
- Publication date Feb 13, 2003
- Harsh D. Sharma
- H03 - BASIC ELECTRONIC CIRCUITRY

Harsh Dev Sharma

Person

Patents Grantslast 30 patents

On-chip measurement of signal state duration

Intelligent delay insertion based on transition

On-chip signal state duration measurement and adjustment

Pulsed dynamic keeper gating

Priority delay insertion circuit

On-chip PLL locked frequency determination method and system

Dividing and distributing the drive strength of a single clock buffer

Use of coupling capacitance to balance skew in a network

Method and a system to distribute clock signals in digital circuits

Method, system and computer product to translate electronic schemat...

Domino to static circuit technique

Method for controlling delays in silicon on insulator circuits

Method and device for the reduction of latch insertion delay

Reduced power dynamic logic circuit that inhibits reevaluation of s...

Patents Applicationslast 30 patents

On-chip signal state duration measurement and adjustment

Pulsed dynamic keeper gating

On-chip measurement of signal state duration

Dividing and distributing the drive strength of a single clock buffer

Template based clock routing and balancing

On-chip PLL locked frequency determination method and system

Use of coupling capacitance to balance skew in a network

Method and a system to distribute clock signals in digital circuits

Method, system and computer product to translate electronic schemat...

Zero-skew transition detection circuit

Intelligent delay insertion based on transition

Priority delay insertion circuit