Helmut Kohler

Person

Moensheim, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Retrieving odd net topology in hierarchical circuit designs
- Patent number 9,064,074
- Issue date Jun 23, 2015
- International Business Machines Corporation
- Joerg Kayser
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Chip circuit for combined and data compressed FIFO arbitration for...
- Patent number 7,675,930
- Issue date Mar 9, 2010
- International Business Machines Corporaiton
- Francois Abel
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Combined and data compressed FIFO based arbitration for a non-block...
- Patent number 7,379,470
- Issue date May 27, 2008
- International Business Machines Coproration
- Francois Abel
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
IML-stream generated error insertion / FRU isolation
- Patent number 7,107,490
- Issue date Sep 12, 2006
- International Business Machines Corporation
- Andreas Eisenhoffer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Checking data integrity in buffered data transmission
- Patent number 5,694,400
- Issue date Dec 2, 1997
- International Business Machines Corporation
- Gilles Gervais
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for checking the address and contents of a mem...
- Patent number 5,321,706
- Issue date Jun 14, 1994
- International Business Machines Corporation
- Ingemar Holm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High density semiconductor memory module using split finger lead frame
- Patent number 5,227,995
- Issue date Jul 13, 1993
- International Business Machines Corporation
- Erich Klink
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Programmable neural logic device
- Patent number 5,218,245
- Issue date Jun 8, 1993
- International Business Machines Corporation
- Helmut Kohler
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
RETRIEVING ODD NET TOPOLOGY IN HIERARCHICAL CIRCUIT DESIGNS
- Publication number 20130124182
- Publication date May 16, 2013
- International Business Machines Corporation
- Joerg Kayser
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CHIP CIRCUIT FOR COMBINED AND DATA COMPRESSED FIFO ARBITRATION FOR...
- Publication number 20080212577
- Publication date Sep 4, 2008
- International Business Machines Corporation
- Francois Abel
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Combined and data compressed fifo based arbitration for a non-block...
- Publication number 20050099945
- Publication date May 12, 2005
- International Business Machines Corporation
- Francois Abel
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
IML-stream generated error insertion / FRU isolation
- Publication number 20030126503
- Publication date Jul 3, 2003
- International Business Machines Corporation
- Andreas Eisenhoffer
- G06 - COMPUTING CALCULATING COUNTING

Helmut Kohler

Person

Patents Grantslast 30 patents

Retrieving odd net topology in hierarchical circuit designs

Chip circuit for combined and data compressed FIFO arbitration for...

Combined and data compressed FIFO based arbitration for a non-block...

IML-stream generated error insertion / FRU isolation

Checking data integrity in buffered data transmission

Method and apparatus for checking the address and contents of a mem...

High density semiconductor memory module using split finger lead frame

Programmable neural logic device

Patents Applicationslast 30 patents

RETRIEVING ODD NET TOPOLOGY IN HIERARCHICAL CIRCUIT DESIGNS

CHIP CIRCUIT FOR COMBINED AND DATA COMPRESSED FIFO ARBITRATION FOR...

Combined and data compressed fifo based arbitration for a non-block...

IML-stream generated error insertion / FRU isolation