Hemangi Umakant Gajjewar

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
No-enable setup clock gater based on pulse
- Patent number 11,258,446
- Issue date Feb 22, 2022
- Apple Inc.
- Vivekanandan Venugopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power switch multiplexer with configurable overlap
- Patent number 10,908,663
- Issue date Feb 2, 2021
- Apple Inc.
- Victor Zyuban
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Supply tracking delay element in multiple power domain designs
- Patent number 10,833,664
- Issue date Nov 10, 2020
- Apple Inc.
- Greg M. Hess
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pulsed sub-VDD precharging of a bit line
- Patent number 10,453,505
- Issue date Oct 22, 2019
- Apple Inc.
- Greg M. Hess
- G11 - INFORMATION STORAGE
Information Patent Grant
Improving read stability of a semiconductor memory
- Patent number 8,830,783
- Issue date Sep 9, 2014
- ARM Limited
- Sachin Satish Idgunji
- G11 - INFORMATION STORAGE
Information Patent Grant
Write assist in a dual write line semiconductor memory
- Patent number 8,582,389
- Issue date Nov 12, 2013
- ARM Limited
- Hemangi Umakant Gajjewar
- G11 - INFORMATION STORAGE
Information Patent Grant
Power supply detection circuitry and method
- Patent number 8,479,033
- Issue date Jul 2, 2013
- ARM Limited
- Hemangi Umakant Gajjewar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Reducing current leakage in a semiconductor device
- Patent number 8,456,199
- Issue date Jun 4, 2013
- ARM Limited
- Gus Yeung
- G05 - CONTROLLING REGULATING
Information Patent Grant
Controlling voltage levels applied to access devices when accessing...
- Patent number 8,355,276
- Issue date Jan 15, 2013
- ARM Limited
- Sachin Satish Idgunji
- G11 - INFORMATION STORAGE
Information Patent Grant
Redundancy architecture for an integrated circuit memory
- Patent number 8,004,913
- Issue date Aug 23, 2011
- ARM Limited
- Hemangi Umakant Gajjewar
- G11 - INFORMATION STORAGE
Information Patent Grant
Redundancy architecture for an integrated circuit memory
- Patent number 7,924,638
- Issue date Apr 12, 2011
- ARM Limited
- Hemangi Umakant Gajjewar
- G11 - INFORMATION STORAGE
Information Patent Grant
Metal line layout in a memory cell
- Patent number 7,606,057
- Issue date Oct 20, 2009
- ARM Limited
- Karl Lin Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Degeneration technique for designing memory devices
- Patent number 7,523,420
- Issue date Apr 21, 2009
- ARM Limited
- Hemangi Umakant Gajjewar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit memory with write assist
- Patent number 7,324,368
- Issue date Jan 29, 2008
- ARM Limited
- Karl Lin Wang
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
NO-ENABLE SETUP CLOCK GATER BASED ON PULSE
- Publication number 20210344344
- Publication date Nov 4, 2021
- Apple Inc.
- Vivekanandan Venugopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Power Switch Multiplexer with Configurable Overlap
- Publication number 20200387205
- Publication date Dec 10, 2020
- Apple Inc.
- Victor Zyuban
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PULSED SUB-VDD PRECHARGING OF A BIT LINE
- Publication number 20190272859
- Publication date Sep 5, 2019
- Apple Inc.
- Greg M. Hess
- G11 - INFORMATION STORAGE
Information Patent Application
SUPPLY TRACKING DELAY ELEMENT IN MULTIPLE POWER DOMAIN DESIGNS
- Publication number 20190052254
- Publication date Feb 14, 2019
- Apple Inc.
- Greg M. Hess
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Write assist in a dual write line semiconductor memory
- Publication number 20120320694
- Publication date Dec 20, 2012
- Hemangi Umakant Gajjewar
- G11 - INFORMATION STORAGE
Information Patent Application
Read stability of a semiconductor memory
- Publication number 20120170390
- Publication date Jul 5, 2012
- ARM Limited
- Sachin Satish Idgunji
- G11 - INFORMATION STORAGE
Information Patent Application
Power supply detection circuitry and method
- Publication number 20110314317
- Publication date Dec 22, 2011
- Hemangi Umakant Gajjewar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Reducing current leakage in a semiconductor device
- Publication number 20110187438
- Publication date Aug 4, 2011
- ARM Limited
- Gus Yeung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Controlling voltage levels applied to access devices when accessing...
- Publication number 20110122712
- Publication date May 26, 2011
- ARM Limited
- Sachin Satish Idgunji
- G11 - INFORMATION STORAGE
Information Patent Application
Redundancy architecture for an integrated circuit memory
- Publication number 20100232241
- Publication date Sep 16, 2010
- ARM Limited
- Hemangi Umakant Gajjewar
- G11 - INFORMATION STORAGE
Information Patent Application
Redundancy architecture for an integrated circuit memory
- Publication number 20080259701
- Publication date Oct 23, 2008
- ARM Limited
- Hemangi Umakant Gajjewar
- G11 - INFORMATION STORAGE
Information Patent Application
Degeneration technique for designing memory devices
- Publication number 20080046856
- Publication date Feb 21, 2008
- ARM Limited
- Hemangi Umakant Gajjewar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Metal line layout in a memory cell
- Publication number 20070279959
- Publication date Dec 6, 2007
- ARM Limited
- Karl Lin Wang
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated circuit memory with write assist
- Publication number 20070236983
- Publication date Oct 11, 2007
- ARM Limited
- Karl Lin Wang
- G11 - INFORMATION STORAGE

Hemangi Umakant Gajjewar

Person

Patents Grantslast 30 patents

No-enable setup clock gater based on pulse

Power switch multiplexer with configurable overlap

Supply tracking delay element in multiple power domain designs

Pulsed sub-VDD precharging of a bit line

Improving read stability of a semiconductor memory

Write assist in a dual write line semiconductor memory

Power supply detection circuitry and method

Reducing current leakage in a semiconductor device

Controlling voltage levels applied to access devices when accessing...

Redundancy architecture for an integrated circuit memory

Redundancy architecture for an integrated circuit memory

Metal line layout in a memory cell

Degeneration technique for designing memory devices

Integrated circuit memory with write assist

Patents Applicationslast 30 patents

NO-ENABLE SETUP CLOCK GATER BASED ON PULSE

Power Switch Multiplexer with Configurable Overlap

PULSED SUB-VDD PRECHARGING OF A BIT LINE

SUPPLY TRACKING DELAY ELEMENT IN MULTIPLE POWER DOMAIN DESIGNS

Write assist in a dual write line semiconductor memory

Read stability of a semiconductor memory

Power supply detection circuitry and method

Reducing current leakage in a semiconductor device

Controlling voltage levels applied to access devices when accessing...

Redundancy architecture for an integrated circuit memory

Redundancy architecture for an integrated circuit memory

Degeneration technique for designing memory devices

Metal line layout in a memory cell

Integrated circuit memory with write assist