Hemen R. Shah

Person

South Burlington, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and systems of powering on integrated circuit
- Patent number 8,016,482
- Issue date Sep 13, 2011
- International Business Machines Corporation
- Igor Arsovski
- G05 - CONTROLLING REGULATING
Information Patent Grant
Critical path redundant logic for mitigation of hardware across chi...
- Patent number 7,898,286
- Issue date Mar 1, 2011
- International Business Machines Corporation
- Igor Arsovski
- G01 - MEASURING TESTING
Information Patent Grant
Transition balancing for noise reduction/Di/Dt reduction during des...
- Patent number 7,823,107
- Issue date Oct 26, 2010
- International Business Machines Corporation
- Igor Arsovski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Design structures of powering on integrated circuit
- Patent number 7,716,007
- Issue date May 11, 2010
- International Business Machines Corporation
- Igor Arsovski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transition balancing for noise reduction /Di/Dt reduction during de...
- Patent number 7,643,591
- Issue date Jan 5, 2010
- International Business Machines Corproation
- Igor Arsovski
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Design structures, method and systems of powering on integrated cir...
- Patent number 7,483,806
- Issue date Jan 27, 2009
- International Business Machines Corporation
- Igor Arsovski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
No latency pipeline
- Patent number 5,532,970
- Issue date Jul 2, 1996
- Edward Butler
- G11 - INFORMATION STORAGE
Information Patent Grant
High performance extended data out
- Patent number 5,490,114
- Issue date Feb 6, 1996
- International Business Machines Corporation
- Edward Butler
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Critical Path Redundant Logic for Mitigation of Hardware Across Chi...
- Publication number 20100201377
- Publication date Aug 12, 2010
- International Business Machines Corporation
- Igor ARSOVSKI
- G01 - MEASURING TESTING
Information Patent Application
Transition Balancing For Noise Reduction/Di/Dt Reduction During Des...
- Publication number 20090106724
- Publication date Apr 23, 2009
- Igor Arsovski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHIFTING INACTIVE CLOCK EDGE FOR NOISE REDUCTION
- Publication number 20090102529
- Publication date Apr 23, 2009
- International Business Machines Corporation
- Igor Arsovski
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
STRUCTURES OF POWERING ON INTEGRATED CIRCUIT
- Publication number 20090024972
- Publication date Jan 22, 2009
- International Business Machines Corporation
- Igor Arsovski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEMS OF POWERING ON INTEGRATED CIRCUIT
- Publication number 20090022203
- Publication date Jan 22, 2009
- Igor Arsovski
- G05 - CONTROLLING REGULATING
Information Patent Application
DESIGN STRUCTURES, METHOD AND SYSTEMS OF POWERING ON INTEGRATED CIR...
- Publication number 20090021085
- Publication date Jan 22, 2009
- International Business Machines Corporation
- Igor Arsovski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHIFTING INACTIVE CLOCK EDGE FOR NOISE REDUCTION
- Publication number 20080046772
- Publication date Feb 21, 2008
- International Business Machines Corporation
- Igor Arsovski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSITION BALANCING FOR NOISE REDUCTION /di/dt REDUCTION DURING DE...
- Publication number 20080043890
- Publication date Feb 21, 2008
- Igor Arsovski
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHOD AND APPARATUS FOR DYNAMICALLY MANAGING POWER CONSUMPTIONS OF...
- Publication number 20050265462
- Publication date Dec 1, 2005
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING

Hemen R. Shah

Person

Patents Grantslast 30 patents

Method and systems of powering on integrated circuit

Critical path redundant logic for mitigation of hardware across chi...

Transition balancing for noise reduction/Di/Dt reduction during des...

Design structures of powering on integrated circuit

Transition balancing for noise reduction /Di/Dt reduction during de...

Design structures, method and systems of powering on integrated cir...

No latency pipeline

High performance extended data out

Patents Applicationslast 30 patents

Critical Path Redundant Logic for Mitigation of Hardware Across Chi...

Transition Balancing For Noise Reduction/Di/Dt Reduction During Des...

SHIFTING INACTIVE CLOCK EDGE FOR NOISE REDUCTION

STRUCTURES OF POWERING ON INTEGRATED CIRCUIT

METHOD AND SYSTEMS OF POWERING ON INTEGRATED CIRCUIT

DESIGN STRUCTURES, METHOD AND SYSTEMS OF POWERING ON INTEGRATED CIR...

SHIFTING INACTIVE CLOCK EDGE FOR NOISE REDUCTION

TRANSITION BALANCING FOR NOISE REDUCTION /di/dt REDUCTION DURING DE...

METHOD AND APPARATUS FOR DYNAMICALLY MANAGING POWER CONSUMPTIONS OF...