Henley Liu

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit (IC) structure protection scheme
- Patent number 12,068,257
- Issue date Aug 20, 2024
- Xilinx, Inc.
- Myongseob Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interwafer connection structure for coupling wafers in a wafer stack
- Patent number 11,901,338
- Issue date Feb 13, 2024
- Xilinx, Inc.
- Myongseob Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked silicon package assembly having thermal management
- Patent number 11,355,412
- Issue date Jun 7, 2022
- Xilinx, Inc.
- Jaspreet Singh Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit device with stacked dies having mirrored circuitry
- Patent number 11,205,639
- Issue date Dec 21, 2021
- Xilinx, Inc.
- Myongseob Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
IC die with dummy structures
- Patent number 11,114,344
- Issue date Sep 7, 2021
- Xilinx, Inc.
- Hui-Wen Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Test circuits for testing a die stack
- Patent number 11,054,461
- Issue date Jul 6, 2021
- Xilinx, Inc.
- Nui Chong
- G01 - MEASURING TESTING
Information Patent Grant
Package integration for high bandwidth memory
- Patent number 10,971,474
- Issue date Apr 6, 2021
- Xilinx, Inc.
- Jaspreet Singh Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package integration for memory devices
- Patent number 10,770,430
- Issue date Sep 8, 2020
- Xilinx, Inc.
- Myongseob Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electronic device apparatus with multiple thermally conductive path...
- Patent number 10,720,377
- Issue date Jul 21, 2020
- Xilinx, Inc.
- Gamal Refai-Ahmed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip package assembly with modular core dice
- Patent number 10,692,837
- Issue date Jun 23, 2020
- Xilinx, Inc.
- Myongseob Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit die with in-chip heat sink
- Patent number 10,629,512
- Issue date Apr 21, 2020
- Xilinx, Inc.
- Hong-Tsz Pan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of interconnect for high density 2.5D and 3D integration
- Patent number 10,593,638
- Issue date Mar 17, 2020
- Xilinx, Inc.
- Jaspreet Singh Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Testing system for lid-less integrated circuit packages
- Patent number 10,527,670
- Issue date Jan 7, 2020
- Xilinx, Inc.
- Gamal Refai-Ahmed
- G01 - MEASURING TESTING
Information Patent Grant
Methods and apparatus for thermal interface material (TIM) bond lin...
- Patent number 10,529,645
- Issue date Jan 7, 2020
- Xilinx, Inc.
- Jaspreet Singh Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer edge partial die engineered for stacked die yield
- Patent number 10,431,565
- Issue date Oct 1, 2019
- Xilinx, Inc.
- Myongseob Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip package assembly with enhanced interconnects and method for fa...
- Patent number 10,319,606
- Issue date Jun 11, 2019
- Xilinx, Inc.
- Jaspreet Singh Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuit for and method of testing bond connections between a first...
- Patent number 10,262,911
- Issue date Apr 16, 2019
- Xilinx, Inc.
- Yuqing Gong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shielded wire arrangement for die testing
- Patent number 9,412,674
- Issue date Aug 9, 2016
- Xilinx, Inc.
- Myongseob Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Capacitors within an interposer coupled to supply and ground planes...
- Patent number 9,337,138
- Issue date May 10, 2016
- Xilinx, Inc.
- Khaldoon S. Abugharbieh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of testing a semiconductor structure
- Patent number 8,810,269
- Issue date Aug 19, 2014
- Xilinx, Inc.
- Yuqing Gong
- G01 - MEASURING TESTING
Information Patent Grant
Methods of manufacturing a semiconductor structure
- Patent number 8,802,454
- Issue date Aug 12, 2014
- Xilinx, Inc.
- Arifur Rahman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit with adaptive VGG setting
- Patent number 8,354,671
- Issue date Jan 15, 2013
- Xilinx, Inc.
- Hsung Jai Im
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUIT (IC) Protections
- Publication number 20240145411
- Publication date May 2, 2024
- Xilinx, Inc.
- Myongseob KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR MITIGATING WARPAGE ON STACKED WAFERS
- Publication number 20240038556
- Publication date Feb 1, 2024
- Xilinx, Inc.
- Myongseob KIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERWAFER CONNECTION STRUCTURE FOR COUPLING WAFERS IN A WAFER STACK
- Publication number 20230140675
- Publication date May 4, 2023
- Xilinx, Inc.
- Myongseob KIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT DEVICE WITH STACKED DIES HAVING MIRRORED CIRCUITRY
- Publication number 20210265312
- Publication date Aug 26, 2021
- Xilinx, Inc.
- Myongseob KIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE INTEGRATION FOR MEMORY DEVICES
- Publication number 20200303341
- Publication date Sep 24, 2020
- Xilinx, Inc.
- Myongseob Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRONIC DEVICE APPARATUS WITH MULTIPLE THERMALLY CONDUCTIVE PATH...
- Publication number 20200152546
- Publication date May 14, 2020
- Xilinx, Inc.
- Gamal Refai-Ahmed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED SILICON PACKAGE ASSEMBLY HAVING THERMAL MANAGEMENT
- Publication number 20200105642
- Publication date Apr 2, 2020
- Xilinx, Inc.
- Jaspreet Singh Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT DIE WITH IN-CHIP HEAT SINK
- Publication number 20200006186
- Publication date Jan 2, 2020
- Xilinx, Inc.
- Hong-Tsz Pan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS AND APPARATUS FOR THERMAL INTERFACE MATERIAL (TIM) BOND LIN...
- Publication number 20180358280
- Publication date Dec 13, 2018
- Xilinx, Inc.
- Jaspreet Singh Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TESTING SYSTEM FOR LID-LESS INTEGRATED CIRCUIT PACKAGES
- Publication number 20180284187
- Publication date Oct 4, 2018
- Xilinx, Inc.
- Gamal Refai-Ahmed
- G01 - MEASURING TESTING
Information Patent Application
METHODS OF INTERCONNECT FOR HIGH DENSITY 2.5D AND 3D INTEGRATION
- Publication number 20180286826
- Publication date Oct 4, 2018
- Xilinx, Inc.
- Jaspreet Singh Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF TESTING A SEMICONDUCTOR STRUCTURE
- Publication number 20140091819
- Publication date Apr 3, 2014
- Xilinx, Inc.
- Yuqing Gong
- G01 - MEASURING TESTING

Person

Patents Grantslast 30 patents

Integrated circuit (IC) structure protection scheme

Interwafer connection structure for coupling wafers in a wafer stack

Stacked silicon package assembly having thermal management

Integrated circuit device with stacked dies having mirrored circuitry

IC die with dummy structures

Test circuits for testing a die stack

Package integration for high bandwidth memory

Package integration for memory devices

Electronic device apparatus with multiple thermally conductive path...

Chip package assembly with modular core dice

Integrated circuit die with in-chip heat sink

Methods of interconnect for high density 2.5D and 3D integration

Testing system for lid-less integrated circuit packages

Methods and apparatus for thermal interface material (TIM) bond lin...

Wafer edge partial die engineered for stacked die yield

Chip package assembly with enhanced interconnects and method for fa...

Circuit for and method of testing bond connections between a first...

Shielded wire arrangement for die testing

Capacitors within an interposer coupled to supply and ground planes...

Method of testing a semiconductor structure

Methods of manufacturing a semiconductor structure

Integrated circuit with adaptive VGG setting

Patents Applicationslast 30 patents

INTEGRATED CIRCUIT (IC) Protections

METHOD FOR MITIGATING WARPAGE ON STACKED WAFERS

INTERWAFER CONNECTION STRUCTURE FOR COUPLING WAFERS IN A WAFER STACK

INTEGRATED CIRCUIT DEVICE WITH STACKED DIES HAVING MIRRORED CIRCUITRY

PACKAGE INTEGRATION FOR MEMORY DEVICES

ELECTRONIC DEVICE APPARATUS WITH MULTIPLE THERMALLY CONDUCTIVE PATH...

STACKED SILICON PACKAGE ASSEMBLY HAVING THERMAL MANAGEMENT

INTEGRATED CIRCUIT DIE WITH IN-CHIP HEAT SINK

METHODS AND APPARATUS FOR THERMAL INTERFACE MATERIAL (TIM) BOND LIN...

TESTING SYSTEM FOR LID-LESS INTEGRATED CIRCUIT PACKAGES

METHODS OF INTERCONNECT FOR HIGH DENSITY 2.5D AND 3D INTEGRATION

METHOD OF TESTING A SEMICONDUCTOR STRUCTURE