Henri Fraisse

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Routing in a compilation flow for a heterogeneous multi-core archit...
- Patent number 11,138,019
- Issue date Oct 5, 2021
- Xilinx, Inc.
- Akella Sastry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Resolving timing violations in multi-die circuit designs
- Patent number 10,747,929
- Issue date Aug 18, 2020
- Xilinx, Inc.
- Henri Fraisse
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Regularity of fabrics in programmable logic devices
- Patent number 10,726,181
- Issue date Jul 28, 2020
- Xilinx, Inc.
- Martin L. Voogel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Routing circuit designs for implementation using a programmable net...
- Patent number 10,628,547
- Issue date Apr 21, 2020
- Xilinx, Inc.
- Ian A. Swarbrick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Performing placement and routing concurrently
- Patent number 10,614,191
- Issue date Apr 7, 2020
- Xilinx, Inc.
- Henri Fraisse
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placing and routing an interface portion and a main portion of a ci...
- Patent number 10,503,861
- Issue date Dec 10, 2019
- Xilinx, Inc.
- Dinesh D. Gaitonde
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Incremental routing for circuit designs using a SAT router
- Patent number 10,445,456
- Issue date Oct 15, 2019
- Xilinx, Inc.
- Henri Fraisse
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and circuits for preventing hold time violations
- Patent number 9,954,534
- Issue date Apr 24, 2018
- Xilinx, Inc.
- Ilya K. Ganusov
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Channel selection in multi-channel switching network
- Patent number 9,935,870
- Issue date Apr 3, 2018
- Xilinx, Inc.
- Henri Fraisse
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Rotated integrated circuit die and chip packages having the same
- Patent number 9,882,562
- Issue date Jan 30, 2018
- Xilinx, Inc.
- Martin L. Voogel
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Folding duplicate instances of modules in a circuit design
- Patent number 9,875,330
- Issue date Jan 23, 2018
- Xilinx, Inc.
- Ilya K. Ganusov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Combining logic elements into pairs in a circuit design system
- Patent number 9,235,671
- Issue date Jan 12, 2016
- Xilinx, Inc.
- Henri Fraisse
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHODS AND CIRCUITS FOR PREVENTING HOLD TIME VIOLATIONS
- Publication number 20180083633
- Publication date Mar 22, 2018
- Xilinx, Inc.
- Ilya K. Ganusov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CHANNEL SELECTION IN MULTI-CHANNEL SWITCHING NETWORK
- Publication number 20170207998
- Publication date Jul 20, 2017
- Xilinx, Inc.
- Henri Fraisse
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
FOLDING DUPLICATE INSTANCES OF MODULES IN A CIRCUIT DESIGN
- Publication number 20170161419
- Publication date Jun 8, 2017
- Xilinx, Inc.
- Ilya K. Ganusov
- G06 - COMPUTING CALCULATING COUNTING

Henri Fraisse

Person

Patents Grantslast 30 patents

Routing in a compilation flow for a heterogeneous multi-core archit...

Resolving timing violations in multi-die circuit designs

Regularity of fabrics in programmable logic devices

Routing circuit designs for implementation using a programmable net...

Performing placement and routing concurrently

Placing and routing an interface portion and a main portion of a ci...

Incremental routing for circuit designs using a SAT router

Methods and circuits for preventing hold time violations

Channel selection in multi-channel switching network

Rotated integrated circuit die and chip packages having the same

Folding duplicate instances of modules in a circuit design

Combining logic elements into pairs in a circuit design system

Patents Applicationslast 30 patents

METHODS AND CIRCUITS FOR PREVENTING HOLD TIME VIOLATIONS

CHANNEL SELECTION IN MULTI-CHANNEL SWITCHING NETWORK

FOLDING DUPLICATE INSTANCES OF MODULES IN A CIRCUIT DESIGN