Henry A. Om'mani

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Memory cell array with row direction gap between erase gate lines a...
- Patent number 12,131,786
- Issue date Oct 29, 2024
- Silicon Storage Technology, Inc.
- Louisa Schneider
- G11 - INFORMATION STORAGE
Information Patent Grant
Ultra-precise tuning of analog neural memory cells in a deep learni...
- Patent number 11,393,535
- Issue date Jul 19, 2022
- Silicon Storage Technology, Inc.
- Steven Lemke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of forming a self-aligned stack gate structure for use in a...
- Patent number 9,570,581
- Issue date Feb 14, 2017
- Silicon Storage Technology, Inc.
- Willem-Jan Toren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned stack gate structure for use in a non-volatile memory...
- Patent number 9,330,922
- Issue date May 3, 2016
- Silicon Storage Technology, Inc.
- Willem-Jan Toren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of operating a split gate flash memory cell with coupling gate
- Patent number 9,245,638
- Issue date Jan 26, 2016
- Silicon Storage Technology, Inc.
- Nhan Do
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of operating a split gate flash memory cell with coupling gate
- Patent number 8,711,636
- Issue date Apr 29, 2014
- Silicon Storage Technology, Inc.
- Nhan Do
- G11 - INFORMATION STORAGE
Information Patent Grant
Array of split gate non-volatile floating gate memory cells having...
- Patent number 8,513,728
- Issue date Aug 20, 2013
- Silicon Storage Technology, Inc.
- Parviz Ghazavi
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM AND METHOD FOR IMPLEMENTING TEMPERATURE COMPENSATION IN A ME...
- Publication number 20250085884
- Publication date Mar 13, 2025
- Silicon Storage Technology here.
- Gilles Festes
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CELL ARRAY WITH ROW DIRECTION GAP BETWEEN ERASE GATE LINES A...
- Publication number 20240257880
- Publication date Aug 1, 2024
- Silicon Storage Technology, Inc.
- Louisa Schneider
- G11 - INFORMATION STORAGE
Information Patent Application
ULTRA-PRECISE TUNING OF NEURAL MEMORY CELLS
- Publication number 20220336020
- Publication date Oct 20, 2022
- Silicon Storage Technology, Inc.
- Steven Lemke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ULTRA-PRECISE TUNING OF ANALOG NEURAL MEMORY CELLS IN A DEEP LEARNI...
- Publication number 20210264983
- Publication date Aug 26, 2021
- Silicon Storage Technology, Inc.
- Steven Lemke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of Forming A Self-Aligned Stack Gate Structure For Use In A...
- Publication number 20160225878
- Publication date Aug 4, 2016
- Silicon Storage Technology, Inc.
- Willem-Jan Toren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method Of Operating A Split Gate Flash Memory Cell With Coupling Gate
- Publication number 20140198578
- Publication date Jul 17, 2014
- Silicon Storage Technology, Inc.
- Nhan Do
- G11 - INFORMATION STORAGE
Information Patent Application
Self-Aligned Stack Gate Structure For Use In A Non-volatile Memory...
- Publication number 20130234223
- Publication date Sep 12, 2013
- Willem-Jan Toren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Array Of Split Gate Non-volatile Floating Gate Memory Cells Having...
- Publication number 20130126958
- Publication date May 23, 2013
- Silicon Storage Technology, Inc.
- Parviz Ghazavi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method Of Operating A Split Gate Flash Memory Cell With Coupling Gate
- Publication number 20130121085
- Publication date May 16, 2013
- Nhan Do
- G11 - INFORMATION STORAGE

Henry A. Om'mani

Person

Patents Grantslast 30 patents

Memory cell array with row direction gap between erase gate lines a...

Ultra-precise tuning of analog neural memory cells in a deep learni...

Method of forming a self-aligned stack gate structure for use in a...

Self-aligned stack gate structure for use in a non-volatile memory...

Method of operating a split gate flash memory cell with coupling gate

Method of operating a split gate flash memory cell with coupling gate

Array of split gate non-volatile floating gate memory cells having...

Patents Applicationslast 30 patents

SYSTEM AND METHOD FOR IMPLEMENTING TEMPERATURE COMPENSATION IN A ME...

MEMORY CELL ARRAY WITH ROW DIRECTION GAP BETWEEN ERASE GATE LINES A...

ULTRA-PRECISE TUNING OF NEURAL MEMORY CELLS

ULTRA-PRECISE TUNING OF ANALOG NEURAL MEMORY CELLS IN A DEEP LEARNI...

Method of Forming A Self-Aligned Stack Gate Structure For Use In A...

Method Of Operating A Split Gate Flash Memory Cell With Coupling Gate

Self-Aligned Stack Gate Structure For Use In A Non-volatile Memory...

Array Of Split Gate Non-volatile Floating Gate Memory Cells Having...

Method Of Operating A Split Gate Flash Memory Cell With Coupling Gate