Henry Chung

Person

Hsinchu, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Method of reducing pattern pitch in integrated circuits
- Patent number 7,105,099
- Issue date Sep 12, 2006
- Macronix International Co., Ltd.
- Henry Chung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating read only memory including a first and secon...
- Patent number 6,998,316
- Issue date Feb 14, 2006
- Macronix International Co, Ltd.
- Tahorng Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for defining a minimum pitch in an integrated circuit beyond...
- Patent number 6,955,961
- Issue date Oct 18, 2005
- Macronix International Co., Ltd.
- Henry Chung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Patterning method for fabricating integrated circuit
- Patent number 6,946,400
- Issue date Sep 20, 2005
- Macronix International Co., Ltd.
- Henry Chung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabrication method of sub-resolution pitch for integrated circuits
- Patent number 6,867,116
- Issue date Mar 15, 2005
- Macronix International Co., Ltd.
- Henry Chung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Use of sacrificial inorganic dielectrics for dual damascene process...
- Patent number 6,812,131
- Issue date Nov 2, 2004
- Honeywell International Inc.
- Joseph Travis Kennedy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual salicides for integrated circuits
- Patent number 6,809,018
- Issue date Oct 26, 2004
- Macronix International Co., Ltd.
- Henry Wei-Ming Chung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
[Method to relax alignment accuracy requirement in fabricat...
- Patent number 6,790,743
- Issue date Sep 14, 2004
- Macronix International Co., Ltd.
- Henry Chung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for reducing pitch
- Patent number 6,774,051
- Issue date Aug 10, 2004
- Macronix International Co., Ltd.
- Chia-Chi Chung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for reducing dimensions between patterns on a photoresist
- Patent number 6,750,150
- Issue date Jun 15, 2004
- Macronix International Co., Ltd.
- Henry Wei-Ming Chung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating read only memory including forming masking l...
- Patent number 6,734,064
- Issue date May 11, 2004
- Macronix International Co., Ltd.
- Tahorng Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Coding method for mask ROM
- Patent number 6,713,354
- Issue date Mar 30, 2004
- Macronix International Co., Ltd.
- Henry Chung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing an array structure in integrated circuits
- Patent number 6,709,923
- Issue date Mar 23, 2004
- Macronix International Co., Ltd.
- Henry Wei-Ming Chung
- B65 - CONVEYING PACKING STORING HANDLING THIN OR FILAMENTARY MATERIAL
Information Patent Grant
Method for forming interconnection structure in an integration circuit
- Patent number 6,642,139
- Issue date Nov 4, 2003
- Macronix International Co., Ltd.
- Henry Chung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned metal-insulator-metal capacitor for integrated circuits
- Patent number 6,472,124
- Issue date Oct 29, 2002
- Macronix International Co., Ltd.
- Henry Chung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming self-aligned mask read only memory by dual damas...
- Patent number 6,403,424
- Issue date Jun 11, 2002
- Macronix International Co., Ltd.
- Chung-Yeh Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabrication method of integrated circuits with multiple low dielect...
- Patent number 6,383,912
- Issue date May 7, 2002
- Honeywell International, Inc.
- Henry Chung
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
MOS transistors having low-resistance salicide gates and a self-ali...
- Publication number 20070207602
- Publication date Sep 6, 2007
- MACRONIX INTERNATIONAL CO., LTD
- Henry Wei-Ming Chung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MOS transistors having low-resistance salicide gates and a self-ali...
- Publication number 20060163667
- Publication date Jul 27, 2006
- Henry Wei-Ming Chung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
[METHOD OF REDUCING PATTERN PITCH IN INTEGRATED CIRCUITS]
- Publication number 20060011575
- Publication date Jan 19, 2006
- Henry Chung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
[METHOD FOR FABRICATING READ ONLY MEMORY]
- Publication number 20040161900
- Publication date Aug 19, 2004
- TAHORNG YANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for reducing dimensions between patterns on a photoresist
- Publication number 20040132225
- Publication date Jul 8, 2004
- MACRONIX INTERNATIONAL CO., LTD
- Henry Wei-Ming Chung
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
PATTERNING METHOD FOR FABRICATING INTEGRATED CIRCUIT
- Publication number 20040121597
- Publication date Jun 24, 2004
- Henry Chung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Polysilicon self-aligned contact and a polysilicon common source li...
- Publication number 20040079984
- Publication date Apr 29, 2004
- Hsuan-Ling Kao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and structure of interconnection with anti-reflection coating
- Publication number 20040018697
- Publication date Jan 29, 2004
- Henry Wei-Ming Chung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dual salicides for integrated circuits
- Publication number 20040009652
- Publication date Jan 15, 2004
- Henry Wei-Ming Chung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR MANUFACTURING AN ARRAY STRUCTURE IN INTEGRATED CIRCUITS
- Publication number 20030235950
- Publication date Dec 25, 2003
- MACRONIX INTERNATIONAL CO., LTD
- Henry Wei-Ming Chung
- B65 - CONVEYING PACKING STORING HANDLING THIN OR FILAMENTARY MATERIAL
Information Patent Application
Method for reducing pitch
- Publication number 20030232509
- Publication date Dec 18, 2003
- Chia-Chi Chung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for reducing dimensions between patterns on a hardmask
- Publication number 20030224602
- Publication date Dec 4, 2003
- MACRONIX INTERNATIONAL CO., LTD
- Henry Wei-Ming Chung
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Method for reducing dimensions between patterns on a photomask
- Publication number 20030224254
- Publication date Dec 4, 2003
- MACRONIX INTERNATIONAL CO., LTD
- Henry Wei-Ming Chung
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Method for reducing dimensions between patterns on a photoresist
- Publication number 20030216051
- Publication date Nov 20, 2003
- MACRONIX INTERNATIONAL CO., LTD
- Henry Wei-Ming Chung
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Method of fabricating phase shift mask
- Publication number 20030203285
- Publication date Oct 30, 2003
- Henry Wei-Ming Chung
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Method for fabricating read only memory
- Publication number 20030181013
- Publication date Sep 25, 2003
- TAHORNG YANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for reducing dimensions between patterns on a photoresist
- Publication number 20030082916
- Publication date May 1, 2003
- Henry Wei-Ming Chung
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Advanced interconnection for integrated circuits
- Publication number 20020151165
- Publication date Oct 17, 2002
- Henry Wei-Ming Chung
- H01 - BASIC ELECTRIC ELEMENTS

Henry Chung

Person

Patents Grantslast 30 patents

Method of reducing pattern pitch in integrated circuits

Method for fabricating read only memory including a first and secon...

Method for defining a minimum pitch in an integrated circuit beyond...

Patterning method for fabricating integrated circuit

Fabrication method of sub-resolution pitch for integrated circuits

Use of sacrificial inorganic dielectrics for dual damascene process...

Dual salicides for integrated circuits

&#x0005B;Method to relax alignment accuracy requirement in fabricat...

Method for reducing pitch

Method for reducing dimensions between patterns on a photoresist

Method for fabricating read only memory including forming masking l...

Coding method for mask ROM

Method for manufacturing an array structure in integrated circuits

Method for forming interconnection structure in an integration circuit

Self-aligned metal-insulator-metal capacitor for integrated circuits

Method for forming self-aligned mask read only memory by dual damas...

Fabrication method of integrated circuits with multiple low dielect...

Patents Applicationslast 30 patents

MOS transistors having low-resistance salicide gates and a self-ali...

MOS transistors having low-resistance salicide gates and a self-ali...

[METHOD OF REDUCING PATTERN PITCH IN INTEGRATED CIRCUITS]

[METHOD FOR FABRICATING READ ONLY MEMORY]

Method for reducing dimensions between patterns on a photoresist

PATTERNING METHOD FOR FABRICATING INTEGRATED CIRCUIT

Polysilicon self-aligned contact and a polysilicon common source li...

Method and structure of interconnection with anti-reflection coating

Dual salicides for integrated circuits

METHOD FOR MANUFACTURING AN ARRAY STRUCTURE IN INTEGRATED CIRCUITS

Method for reducing pitch

Method for reducing dimensions between patterns on a hardmask

Method for reducing dimensions between patterns on a photomask

Method for reducing dimensions between patterns on a photoresist

Method of fabricating phase shift mask

Method for fabricating read only memory

Method for reducing dimensions between patterns on a photoresist

Advanced interconnection for integrated circuits

[Method to relax alignment accuracy requirement in fabricat...