Henry Kim

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Omnibus logic element
- Patent number 10,177,766
- Issue date Jan 8, 2019
- Altera Corporation
- James Schleicher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structures for LUT-based arithmetic in PLDs
- Patent number 9,658,830
- Issue date May 23, 2017
- Altera Corporation
- Ketan Padalia
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Omnibus logic element
- Patent number 9,496,875
- Issue date Nov 15, 2016
- Altera Corporation
- James Schleicher
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Omnibus logic element
- Patent number 8,878,567
- Issue date Nov 4, 2014
- Altera Corporation
- James Schleicher
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Structures for LUT-based arithmetic in PLDs
- Patent number 8,788,550
- Issue date Jul 22, 2014
- Altera Corporation
- Ketan Padalia
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Omnibus logic element for packing or fracturing
- Patent number 8,593,174
- Issue date Nov 26, 2013
- Altera Corporation
- James Schleicher
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Omnibus logic element for packing or fracturing
- Patent number 8,237,465
- Issue date Aug 7, 2012
- Altera Corporation
- James Schleicher
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Omnibus logic element for packing or fracturing
- Patent number 7,911,230
- Issue date Mar 22, 2011
- Altera Corporation
- James Schleicher
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Omnibus logic element
- Patent number 7,671,625
- Issue date Mar 2, 2010
- Altera Corporation
- James Schleicher
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Versatile logic element and logic array block
- Patent number 7,671,626
- Issue date Mar 2, 2010
- Altera Corporation
- David M. Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock edge de-skew
- Patent number 7,590,879
- Issue date Sep 15, 2009
- Altera Corporation
- Henry Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structures for LUT-based arithmetic in PLDs
- Patent number 7,558,812
- Issue date Jul 7, 2009
- Altera Corporation
- Ketan Padalia
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Omnibus logic element
- Patent number 7,538,579
- Issue date May 26, 2009
- Altera Corporation
- James Schleicher
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Versatile logic element and logic array block
- Patent number 7,432,734
- Issue date Oct 7, 2008
- Altera Corporation
- David M. Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Versatile logic element and logic array block
- Patent number 7,218,133
- Issue date May 15, 2007
- Altera Corporation
- David M. Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Techniques for controlling on-chip termination resistance using vol...
- Patent number 7,218,155
- Issue date May 15, 2007
- Altera Corporation
- Tzung-Chin Chang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
DLL with adjustable phase shift using processed control signal
- Patent number 7,212,054
- Issue date May 1, 2007
- Altera Corporation
- Tzung-chin Chang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and method for controlling a delay chain
- Patent number 7,205,802
- Issue date Apr 17, 2007
- Altera Corporation
- Bonnie I. Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Omnibus logic element including look up table based logic elements
- Patent number 7,167,022
- Issue date Jan 23, 2007
- Altera Corporation
- James Schleicher
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
DLL with adjustable phase shift using processed control signal
- Patent number 7,091,760
- Issue date Aug 15, 2006
- Altera Corporation
- Tzung-chin Chang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and method for controlling a delay chain
- Patent number 7,030,675
- Issue date Apr 18, 2006
- Altera Corporation
- Bonnie I. Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Versatile logic element and logic array block
- Patent number 6,937,064
- Issue date Aug 30, 2005
- Altera Corporation
- David M. Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
STRUCTURES FOR LUT-BASED ARITHMETIC IN PLDS
- Publication number 20170322775
- Publication date Nov 9, 2017
- Altera Corporation
- Ketan Padalia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VERSATILE LOGIC ELEMENT AND LOGIC ARRAY BLOCK
- Publication number 20070252617
- Publication date Nov 1, 2007
- Altera Corporation
- David M. Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Versatile logic element and logic array block
- Publication number 20050127944
- Publication date Jun 16, 2005
- Altera Corporation
- David M. Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY

Person

Patents Grantslast 30 patents

Omnibus logic element

Structures for LUT-based arithmetic in PLDs

Omnibus logic element

Omnibus logic element

Structures for LUT-based arithmetic in PLDs

Omnibus logic element for packing or fracturing

Omnibus logic element for packing or fracturing

Omnibus logic element for packing or fracturing

Omnibus logic element

Versatile logic element and logic array block

Clock edge de-skew

Structures for LUT-based arithmetic in PLDs

Omnibus logic element

Versatile logic element and logic array block

Versatile logic element and logic array block

Techniques for controlling on-chip termination resistance using vol...

DLL with adjustable phase shift using processed control signal

Apparatus and method for controlling a delay chain

Omnibus logic element including look up table based logic elements

DLL with adjustable phase shift using processed control signal

Apparatus and method for controlling a delay chain

Versatile logic element and logic array block

Patents Applicationslast 30 patents

STRUCTURES FOR LUT-BASED ARITHMETIC IN PLDS

VERSATILE LOGIC ELEMENT AND LOGIC ARRAY BLOCK

Versatile logic element and logic array block