Henry Law

Person

Los Altos, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Flexible memory architectures for programmable logic devices
- Patent number 7,957,208
- Issue date Jun 7, 2011
- Lattice Semiconductor Corporation
- Howard Tang
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable logic device with power-saving architecture
- Patent number 7,558,143
- Issue date Jul 7, 2009
- Lattice Semiconductor Corporation
- Henry Law
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable logic devices with user non-volatile memory
- Patent number 7,554,358
- Issue date Jun 30, 2009
- Lattice Semiconductor Corporation
- Fabiano Fontana
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Flexible memory architectures for programmable logic devices
- Patent number 7,495,970
- Issue date Feb 24, 2009
- Lattice Semiconductor Corporation
- Howard Tang
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable logic devices with transparent field reconfiguration
- Patent number 7,459,931
- Issue date Dec 2, 2008
- Lattice Semiconductor Corporation
- Howard Tang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device with power-saving architecture
- Patent number 7,376,037
- Issue date May 20, 2008
- Lattice Semiconductor Corporation
- Henry Law
- G11 - INFORMATION STORAGE
Information Patent Grant
High speed CMOS output buffer circuit minimizes propagation delay a...
- Patent number 5,438,278
- Issue date Aug 1, 1995
- Advanced Micro Devices, Inc.
- Jack T. Wong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High speed NOR gate with small output voltage swings
- Patent number 5,432,463
- Issue date Jul 11, 1995
- Advanced Micro Devices, Inc.
- Jack T. Wong
- H03 - BASIC ELECTRONIC CIRCUITRY

Person

Patents Grantslast 30 patents

Flexible memory architectures for programmable logic devices

Programmable logic device with power-saving architecture

Programmable logic devices with user non-volatile memory

Flexible memory architectures for programmable logic devices

Programmable logic devices with transparent field reconfiguration

Programmable logic device with power-saving architecture

High speed CMOS output buffer circuit minimizes propagation delay a...

High speed NOR gate with small output voltage swings